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Merge commit b320441c04 ("Merge tag 'tty-6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty") into tty-next 

We need the serial-core fixes in here as well.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman 2023-08-20 14:29:37 +02:00
parent e67d7f60d2 b320441c04
commit 642073c306
813 changed files with 8050 additions and 3841 deletions
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2
.mailmap
View File

@ -538,6 +538,8 @@ Shuah Khan <shuah@kernel.org> <shuah.kh@samsung.com>
Sibi Sankar <quic_sibis@quicinc.com> <sibis@codeaurora.org> Sibi Sankar <quic_sibis@quicinc.com> <sibis@codeaurora.org>
Sid Manning <quic_sidneym@quicinc.com> <sidneym@codeaurora.org> Sid Manning <quic_sidneym@quicinc.com> <sidneym@codeaurora.org>
Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu> Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu>
Simon Horman <horms@kernel.org> <simon.horman@corigine.com>
Simon Horman <horms@kernel.org> <simon.horman@netronome.com>
Simon Kelley <simon@thekelleys.org.uk> Simon Kelley <simon@thekelleys.org.uk>
Sricharan Ramabadhran <quic_srichara@quicinc.com> <sricharan@codeaurora.org> Sricharan Ramabadhran <quic_srichara@quicinc.com> <sricharan@codeaurora.org>
Srinivas Ramana <quic_sramana@quicinc.com> <sramana@codeaurora.org> Srinivas Ramana <quic_sramana@quicinc.com> <sramana@codeaurora.org>

15
Documentation/ABI/testing/sysfs-bus-cxl
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@ -82,7 +82,12 @@ Description:
whether it resides in persistent capacity, volatile capacity, whether it resides in persistent capacity, volatile capacity,
or the LSA, is made permanently unavailable by whatever means or the LSA, is made permanently unavailable by whatever means
is appropriate for the media type. This functionality requires is appropriate for the media type. This functionality requires
the device to be not be actively decoding any HPA ranges. the device to be disabled, that is, not actively decoding any
HPA ranges. This permits avoiding explicit global CPU cache
management, relying instead for it to be done when a region
transitions between software programmed and hardware committed
states. If this file is not present, then there is no hardware
support for the operation.
What /sys/bus/cxl/devices/memX/security/erase What /sys/bus/cxl/devices/memX/security/erase
@ -92,7 +97,13 @@ Contact: linux-cxl@vger.kernel.org
Description: Description:
(WO) Write a boolean 'true' string value to this attribute to (WO) Write a boolean 'true' string value to this attribute to
secure erase user data by changing the media encryption keys for secure erase user data by changing the media encryption keys for
all user data areas of the device. all user data areas of the device. This functionality requires
the device to be disabled, that is, not actively decoding any
HPA ranges. This permits avoiding explicit global CPU cache
management, relying instead for it to be done when a region
transitions between software programmed and hardware committed
states. If this file is not present, then there is no hardware
support for the operation.
What: /sys/bus/cxl/devices/memX/firmware/ What: /sys/bus/cxl/devices/memX/firmware/

15
Documentation/ABI/testing/sysfs-devices-system-cpu
View File

@ -513,17 +513,18 @@ Description: information about CPUs heterogeneity.
cpu_capacity: capacity of cpuX. cpu_capacity: capacity of cpuX.
What: /sys/devices/system/cpu/vulnerabilities What: /sys/devices/system/cpu/vulnerabilities
/sys/devices/system/cpu/vulnerabilities/meltdown /sys/devices/system/cpu/vulnerabilities/gather_data_sampling
/sys/devices/system/cpu/vulnerabilities/spectre_v1 /sys/devices/system/cpu/vulnerabilities/itlb_multihit
/sys/devices/system/cpu/vulnerabilities/spectre_v2
/sys/devices/system/cpu/vulnerabilities/spec_store_bypass
/sys/devices/system/cpu/vulnerabilities/l1tf /sys/devices/system/cpu/vulnerabilities/l1tf
/sys/devices/system/cpu/vulnerabilities/mds /sys/devices/system/cpu/vulnerabilities/mds
/sys/devices/system/cpu/vulnerabilities/srbds /sys/devices/system/cpu/vulnerabilities/meltdown
/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
/sys/devices/system/cpu/vulnerabilities/itlb_multihit
/sys/devices/system/cpu/vulnerabilities/mmio_stale_data /sys/devices/system/cpu/vulnerabilities/mmio_stale_data
/sys/devices/system/cpu/vulnerabilities/retbleed /sys/devices/system/cpu/vulnerabilities/retbleed
/sys/devices/system/cpu/vulnerabilities/spec_store_bypass
/sys/devices/system/cpu/vulnerabilities/spectre_v1
/sys/devices/system/cpu/vulnerabilities/spectre_v2
/sys/devices/system/cpu/vulnerabilities/srbds
/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
Date: January 2018 Date: January 2018
Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
Description: Information about CPU vulnerabilities Description: Information about CPU vulnerabilities

2
Documentation/ABI/testing/sysfs-platform-hidma
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@ -2,7 +2,7 @@ What: /sys/devices/platform/hidma-*/chid
/sys/devices/platform/QCOM8061:*/chid /sys/devices/platform/QCOM8061:*/chid
Date: Dec 2015 Date: Dec 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Contains the ID of the channel within the HIDMA instance. Contains the ID of the channel within the HIDMA instance.
It is used to associate a given HIDMA channel with the It is used to associate a given HIDMA channel with the

20
Documentation/ABI/testing/sysfs-platform-hidma-mgmt
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@ -2,7 +2,7 @@ What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/priority
/sys/devices/platform/QCOM8060:*/chanops/chan*/priority /sys/devices/platform/QCOM8060:*/chanops/chan*/priority
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Contains either 0 or 1 and indicates if the DMA channel is a Contains either 0 or 1 and indicates if the DMA channel is a
low priority (0) or high priority (1) channel. low priority (0) or high priority (1) channel.
@ -11,7 +11,7 @@ What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/weight
/sys/devices/platform/QCOM8060:*/chanops/chan*/weight /sys/devices/platform/QCOM8060:*/chanops/chan*/weight
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Contains 0..15 and indicates the weight of the channel among Contains 0..15 and indicates the weight of the channel among
equal priority channels during round robin scheduling. equal priority channels during round robin scheduling.
@ -20,7 +20,7 @@ What: /sys/devices/platform/hidma-mgmt*/chreset_timeout_cycles
/sys/devices/platform/QCOM8060:*/chreset_timeout_cycles /sys/devices/platform/QCOM8060:*/chreset_timeout_cycles
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Contains the platform specific cycle value to wait after a Contains the platform specific cycle value to wait after a
reset command is issued. If the value is chosen too short, reset command is issued. If the value is chosen too short,
@ -32,7 +32,7 @@ What: /sys/devices/platform/hidma-mgmt*/dma_channels
/sys/devices/platform/QCOM8060:*/dma_channels /sys/devices/platform/QCOM8060:*/dma_channels
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Contains the number of dma channels supported by one instance Contains the number of dma channels supported by one instance
of HIDMA hardware. The value may change from chip to chip. of HIDMA hardware. The value may change from chip to chip.
@ -41,7 +41,7 @@ What: /sys/devices/platform/hidma-mgmt*/hw_version_major
/sys/devices/platform/QCOM8060:*/hw_version_major /sys/devices/platform/QCOM8060:*/hw_version_major
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Version number major for the hardware. Version number major for the hardware.
@ -49,7 +49,7 @@ What: /sys/devices/platform/hidma-mgmt*/hw_version_minor
/sys/devices/platform/QCOM8060:*/hw_version_minor /sys/devices/platform/QCOM8060:*/hw_version_minor
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Version number minor for the hardware. Version number minor for the hardware.
@ -57,7 +57,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_rd_xactions
/sys/devices/platform/QCOM8060:*/max_rd_xactions /sys/devices/platform/QCOM8060:*/max_rd_xactions
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Contains a value between 0 and 31. Maximum number of Contains a value between 0 and 31. Maximum number of
read transactions that can be issued back to back. read transactions that can be issued back to back.
@ -69,7 +69,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_read_request
/sys/devices/platform/QCOM8060:*/max_read_request /sys/devices/platform/QCOM8060:*/max_read_request
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Size of each read request. The value needs to be a power Size of each read request. The value needs to be a power
of two and can be between 128 and 1024. of two and can be between 128 and 1024.
@ -78,7 +78,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_wr_xactions
/sys/devices/platform/QCOM8060:*/max_wr_xactions /sys/devices/platform/QCOM8060:*/max_wr_xactions
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Contains a value between 0 and 31. Maximum number of Contains a value between 0 and 31. Maximum number of
write transactions that can be issued back to back. write transactions that can be issued back to back.
@ -91,7 +91,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_write_request
/sys/devices/platform/QCOM8060:*/max_write_request /sys/devices/platform/QCOM8060:*/max_write_request
Date: Nov 2015 Date: Nov 2015
KernelVersion: 4.4 KernelVersion: 4.4
Contact: "Sinan Kaya <okaya@codeaurora.org>" Contact: "Sinan Kaya <okaya@kernel.org>"
Description: Description:
Size of each write request. The value needs to be a power Size of each write request. The value needs to be a power
of two and can be between 128 and 1024. of two and can be between 128 and 1024.

109
Documentation/admin-guide/hw-vuln/gather_data_sampling.rst Normal file
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@ -0,0 +1,109 @@
.. SPDX-License-Identifier: GPL-2.0
GDS - Gather Data Sampling
==========================
Gather Data Sampling is a hardware vulnerability which allows unprivileged
speculative access to data which was previously stored in vector registers.
Problem
-------
When a gather instruction performs loads from memory, different data elements
are merged into the destination vector register. However, when a gather
instruction that is transiently executed encounters a fault, stale data from
architectural or internal vector registers may get transiently forwarded to the
destination vector register instead. This will allow a malicious attacker to
infer stale data using typical side channel techniques like cache timing
attacks. GDS is a purely sampling-based attack.
The attacker uses gather instructions to infer the stale vector register data.
The victim does not need to do anything special other than use the vector
registers. The victim does not need to use gather instructions to be
vulnerable.
Because the buffers are shared between Hyper-Threads cross Hyper-Thread attacks
are possible.
Attack scenarios
----------------
Without mitigation, GDS can infer stale data across virtually all
permission boundaries:
Non-enclaves can infer SGX enclave data
Userspace can infer kernel data
Guests can infer data from hosts
Guest can infer guest from other guests
Users can infer data from other users
Because of this, it is important to ensure that the mitigation stays enabled in
lower-privilege contexts like guests and when running outside SGX enclaves.
The hardware enforces the mitigation for SGX. Likewise, VMMs should ensure
that guests are not allowed to disable the GDS mitigation. If a host erred and
allowed this, a guest could theoretically disable GDS mitigation, mount an
attack, and re-enable it.
Mitigation mechanism
--------------------
This issue is mitigated in microcode. The microcode defines the following new
bits:
================================ === ============================
IA32_ARCH_CAPABILITIES[GDS_CTRL] R/O Enumerates GDS vulnerability
and mitigation support.
IA32_ARCH_CAPABILITIES[GDS_NO] R/O Processor is not vulnerable.
IA32_MCU_OPT_CTRL[GDS_MITG_DIS] R/W Disables the mitigation
0 by default.
IA32_MCU_OPT_CTRL[GDS_MITG_LOCK] R/W Locks GDS_MITG_DIS=0. Writes
to GDS_MITG_DIS are ignored
Can't be cleared once set.
================================ === ============================
GDS can also be mitigated on systems that don't have updated microcode by
disabling AVX. This can be done by setting gather_data_sampling="force" or
"clearcpuid=avx" on the kernel command-line.
If used, these options will disable AVX use by turning off XSAVE YMM support.
However, the processor will still enumerate AVX support. Userspace that
does not follow proper AVX enumeration to check both AVX *and* XSAVE YMM
support will break.
Mitigation control on the kernel command line
---------------------------------------------
The mitigation can be disabled by setting "gather_data_sampling=off" or
"mitigations=off" on the kernel command line. Not specifying either will default
to the mitigation being enabled. Specifying "gather_data_sampling=force" will
use the microcode mitigation when available or disable AVX on affected systems
where the microcode hasn't been updated to include the mitigation.
GDS System Information
------------------------
The kernel provides vulnerability status information through sysfs. For
GDS this can be accessed by the following sysfs file:
/sys/devices/system/cpu/vulnerabilities/gather_data_sampling
The possible values contained in this file are:
============================== =============================================
Not affected Processor not vulnerable.
Vulnerable Processor vulnerable and mitigation disabled.
Vulnerable: No microcode Processor vulnerable and microcode is missing
mitigation.
Mitigation: AVX disabled,
no microcode Processor is vulnerable and microcode is missing
mitigation. AVX disabled as mitigation.
Mitigation: Microcode Processor is vulnerable and mitigation is in
effect.
Mitigation: Microcode (locked) Processor is vulnerable and mitigation is in
effect and cannot be disabled.
Unknown: Dependent on
hypervisor status Running on a virtual guest processor that is
affected but with no way to know if host
processor is mitigated or vulnerable.
============================== =============================================
GDS Default mitigation
----------------------
The updated microcode will enable the mitigation by default. The kernel's
default action is to leave the mitigation enabled.

14
Documentation/admin-guide/hw-vuln/index.rst
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@ -13,9 +13,11 @@ are configurable at compile, boot or run time.
l1tf l1tf
mds mds
tsx_async_abort tsx_async_abort
multihit.rst multihit
special-register-buffer-data-sampling.rst special-register-buffer-data-sampling
core-scheduling.rst core-scheduling
l1d_flush.rst l1d_flush
processor_mmio_stale_data.rst processor_mmio_stale_data
cross-thread-rsb.rst cross-thread-rsb
srso
gather_data_sampling

150
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@ -0,0 +1,150 @@
.. SPDX-License-Identifier: GPL-2.0
Speculative Return Stack Overflow (SRSO)
========================================
This is a mitigation for the speculative return stack overflow (SRSO)
vulnerability found on AMD processors. The mechanism is by now the well
known scenario of poisoning CPU functional units - the Branch Target
Buffer (BTB) and Return Address Predictor (RAP) in this case - and then
tricking the elevated privilege domain (the kernel) into leaking
sensitive data.
AMD CPUs predict RET instructions using a Return Address Predictor (aka
Return Address Stack/Return Stack Buffer). In some cases, a non-architectural
CALL instruction (i.e., an instruction predicted to be a CALL but is
not actually a CALL) can create an entry in the RAP which may be used
to predict the target of a subsequent RET instruction.
The specific circumstances that lead to this varies by microarchitecture
but the concern is that an attacker can mis-train the CPU BTB to predict
non-architectural CALL instructions in kernel space and use this to
control the speculative target of a subsequent kernel RET, potentially
leading to information disclosure via a speculative side-channel.
The issue is tracked under CVE-2023-20569.
Affected processors
-------------------
AMD Zen, generations 1-4. That is, all families 0x17 and 0x19. Older
processors have not been investigated.
System information and options
------------------------------
First of all, it is required that the latest microcode be loaded for
mitigations to be effective.
The sysfs file showing SRSO mitigation status is:
/sys/devices/system/cpu/vulnerabilities/spec_rstack_overflow
The possible values in this file are:
* 'Not affected':
The processor is not vulnerable
* 'Vulnerable: no microcode':
The processor is vulnerable, no microcode extending IBPB
functionality to address the vulnerability has been applied.
* 'Mitigation: microcode':
Extended IBPB functionality microcode patch has been applied. It does
not address User->Kernel and Guest->Host transitions protection but it
does address User->User and VM->VM attack vectors.
Note that User->User mitigation is controlled by how the IBPB aspect in
the Spectre v2 mitigation is selected:
* conditional IBPB:
where each process can select whether it needs an IBPB issued
around it PR_SPEC_DISABLE/_ENABLE etc, see :doc:`spectre`
* strict:
i.e., always on - by supplying spectre_v2_user=on on the kernel
command line
(spec_rstack_overflow=microcode)
* 'Mitigation: safe RET':
Software-only mitigation. It complements the extended IBPB microcode
patch functionality by addressing User->Kernel and Guest->Host
transitions protection.
Selected by default or by spec_rstack_overflow=safe-ret
* 'Mitigation: IBPB':
Similar protection as "safe RET" above but employs an IBPB barrier on
privilege domain crossings (User->Kernel, Guest->Host).
(spec_rstack_overflow=ibpb)
* 'Mitigation: IBPB on VMEXIT':
Mitigation addressing the cloud provider scenario - the Guest->Host
transitions only.
(spec_rstack_overflow=ibpb-vmexit)
In order to exploit vulnerability, an attacker needs to:
- gain local access on the machine
- break kASLR
- find gadgets in the running kernel in order to use them in the exploit
- potentially create and pin an additional workload on the sibling
thread, depending on the microarchitecture (not necessary on fam 0x19)
- run the exploit
Considering the performance implications of each mitigation type, the
default one is 'Mitigation: safe RET' which should take care of most
attack vectors, including the local User->Kernel one.
As always, the user is advised to keep her/his system up-to-date by
applying software updates regularly.
The default setting will be reevaluated when needed and especially when
new attack vectors appear.
As one can surmise, 'Mitigation: safe RET' does come at the cost of some
performance depending on the workload. If one trusts her/his userspace
and does not want to suffer the performance impact, one can always
disable the mitigation with spec_rstack_overflow=off.
Similarly, 'Mitigation: IBPB' is another full mitigation type employing
an indrect branch prediction barrier after having applied the required
microcode patch for one's system. This mitigation comes also at
a performance cost.
Mitigation: safe RET
--------------------
The mitigation works by ensuring all RET instructions speculate to
a controlled location, similar to how speculation is controlled in the
retpoline sequence. To accomplish this, the __x86_return_thunk forces
the CPU to mispredict every function return using a 'safe return'
sequence.
To ensure the safety of this mitigation, the kernel must ensure that the
safe return sequence is itself free from attacker interference. In Zen3
and Zen4, this is accomplished by creating a BTB alias between the
untraining function srso_alias_untrain_ret() and the safe return
function srso_alias_safe_ret() which results in evicting a potentially
poisoned BTB entry and using that safe one for all function returns.
In older Zen1 and Zen2, this is accomplished using a reinterpretation
technique similar to Retbleed one: srso_untrain_ret() and
srso_safe_ret().

6
Documentation/admin-guide/kdump/vmcoreinfo.rst
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@ -624,3 +624,9 @@ Used to get the correct ranges:
* VMALLOC_START ~ VMALLOC_END : vmalloc() / ioremap() space. * VMALLOC_START ~ VMALLOC_END : vmalloc() / ioremap() space.
* VMEMMAP_START ~ VMEMMAP_END : vmemmap space, used for struct page array. * VMEMMAP_START ~ VMEMMAP_END : vmemmap space, used for struct page array.
* KERNEL_LINK_ADDR : start address of Kernel link and BPF * KERNEL_LINK_ADDR : start address of Kernel link and BPF
va_kernel_pa_offset
-------------------
Indicates the offset between the kernel virtual and physical mappings.
Used to translate virtual to physical addresses.

58
Documentation/admin-guide/kernel-parameters.txt
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@ -1623,6 +1623,26 @@
Format: off | on Format: off | on
default: on default: on
gather_data_sampling=
[X86,INTEL] Control the Gather Data Sampling (GDS)
mitigation.
Gather Data Sampling is a hardware vulnerability which
allows unprivileged speculative access to data which was
previously stored in vector registers.
This issue is mitigated by default in updated microcode.
The mitigation may have a performance impact but can be
disabled. On systems without the microcode mitigation
disabling AVX serves as a mitigation.
force: Disable AVX to mitigate systems without
microcode mitigation. No effect if the microcode
mitigation is present. Known to cause crashes in
userspace with buggy AVX enumeration.
off: Disable GDS mitigation.
gcov_persist= [GCOV] When non-zero (default), profiling data for gcov_persist= [GCOV] When non-zero (default), profiling data for
kernel modules is saved and remains accessible via kernel modules is saved and remains accessible via
debugfs, even when the module is unloaded/reloaded. debugfs, even when the module is unloaded/reloaded.
@ -3273,24 +3293,25 @@
Disable all optional CPU mitigations. This Disable all optional CPU mitigations. This
improves system performance, but it may also improves system performance, but it may also
expose users to several CPU vulnerabilities. expose users to several CPU vulnerabilities.
Equivalent to: nopti [X86,PPC] Equivalent to: if nokaslr then kpti=0 [ARM64]
if nokaslr then kpti=0 [ARM64] gather_data_sampling=off [X86]
nospectre_v1 [X86,PPC] kvm.nx_huge_pages=off [X86]
nobp=0 [S390]
nospectre_v2 [X86,PPC,S390,ARM64]
spectre_v2_user=off [X86]
spec_store_bypass_disable=off [X86,PPC]
ssbd=force-off [ARM64]
nospectre_bhb [ARM64]
l1tf=off [X86] l1tf=off [X86]
mds=off [X86] mds=off [X86]
tsx_async_abort=off [X86] mmio_stale_data=off [X86]
kvm.nx_huge_pages=off [X86]
srbds=off [X86,INTEL]
no_entry_flush [PPC] no_entry_flush [PPC]
no_uaccess_flush [PPC] no_uaccess_flush [PPC]
mmio_stale_data=off [X86] nobp=0 [S390]
nopti [X86,PPC]
nospectre_bhb [ARM64]
nospectre_v1 [X86,PPC]
nospectre_v2 [X86,PPC,S390,ARM64]
retbleed=off [X86] retbleed=off [X86]
spec_store_bypass_disable=off [X86,PPC]
spectre_v2_user=off [X86]
srbds=off [X86,INTEL]
ssbd=force-off [ARM64]
tsx_async_abort=off [X86]
Exceptions: Exceptions:
This does not have any effect on This does not have any effect on
@ -5875,6 +5896,17 @@
Not specifying this option is equivalent to Not specifying this option is equivalent to
spectre_v2_user=auto. spectre_v2_user=auto.
spec_rstack_overflow=
[X86] Control RAS overflow mitigation on AMD Zen CPUs
off - Disable mitigation
microcode - Enable microcode mitigation only
safe-ret - Enable sw-only safe RET mitigation (default)
ibpb - Enable mitigation by issuing IBPB on
kernel entry
ibpb-vmexit - Issue IBPB only on VMEXIT
(cloud-specific mitigation)
spec_store_bypass_disable= spec_store_bypass_disable=
[HW] Control Speculative Store Bypass (SSB) Disable mitigation [HW] Control Speculative Store Bypass (SSB) Disable mitigation
(Speculative Store Bypass vulnerability) (Speculative Store Bypass vulnerability)

3
Documentation/devicetree/bindings/iio/addac/adi,ad74115.yaml
View File

@ -216,7 +216,6 @@ properties:
description: Whether to enable burnout current for EXT1. description: Whether to enable burnout current for EXT1.
adi,ext1-burnout-current-nanoamp: adi,ext1-burnout-current-nanoamp:
$ref: /schemas/types.yaml#/definitions/uint32
description: description:
Burnout current in nanoamps to be applied to EXT1. Burnout current in nanoamps to be applied to EXT1.
enum: [0, 50, 500, 1000, 10000] enum: [0, 50, 500, 1000, 10000]
@ -233,7 +232,6 @@ properties:
description: Whether to enable burnout current for EXT2. description: Whether to enable burnout current for EXT2.
adi,ext2-burnout-current-nanoamp: adi,ext2-burnout-current-nanoamp:
$ref: /schemas/types.yaml#/definitions/uint32
description: Burnout current in nanoamps to be applied to EXT2. description: Burnout current in nanoamps to be applied to EXT2.
enum: [0, 50, 500, 1000, 10000] enum: [0, 50, 500, 1000, 10000]
default: 0 default: 0
@ -249,7 +247,6 @@ properties:
description: Whether to enable burnout current for VIOUT. description: Whether to enable burnout current for VIOUT.
adi,viout-burnout-current-nanoamp: adi,viout-burnout-current-nanoamp:
$ref: /schemas/types.yaml#/definitions/uint32
description: Burnout current in nanoamps to be applied to VIOUT. description: Burnout current in nanoamps to be applied to VIOUT.
enum: [0, 1000, 10000] enum: [0, 1000, 10000]
default: 0 default: 0

7
Documentation/devicetree/bindings/net/mediatek,net.yaml
View File

@ -293,7 +293,7 @@ allOf:
patternProperties: patternProperties:
"^mac@[0-1]$": "^mac@[0-1]$":
type: object type: object
additionalProperties: false unevaluatedProperties: false
allOf: allOf:
- $ref: ethernet-controller.yaml# - $ref: ethernet-controller.yaml#
description: description:
@ -305,14 +305,9 @@ patternProperties:
reg: reg:
maxItems: 1 maxItems: 1
phy-handle: true
phy-mode: true
required: required:
- reg - reg
- compatible - compatible
- phy-handle
required: required:
- compatible - compatible

10
Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
View File

@ -91,12 +91,18 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle $ref: /schemas/types.yaml#/definitions/phandle
tx_delay: tx_delay:
description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default. description: Delay value for TXD timing.
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 0x7F
default: 0x30
rx_delay: rx_delay:
description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default. description: Delay value for RXD timing.
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 0x7F
default: 0x10
phy-supply: phy-supply:
description: PHY regulator description: PHY regulator

2
Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
View File

@ -87,7 +87,7 @@ $defs:
emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0, emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0,
emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio,
emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3,
gcc_gp4, gcc_gp5, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, gcc_gp4, gcc_gp5, gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c,
jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3, jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3,
mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8,
mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,

4
Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
View File

@ -16,13 +16,15 @@ properties:
- enum: - enum:
- atmel,at91rm9200-usart - atmel,at91rm9200-usart
- atmel,at91sam9260-usart - atmel,at91sam9260-usart
- microchip,sam9x60-usart
- items: - items:
- const: atmel,at91rm9200-dbgu - const: atmel,at91rm9200-dbgu
- const: atmel,at91rm9200-usart - const: atmel,at91rm9200-usart
- items: - items:
- const: atmel,at91sam9260-dbgu - const: atmel,at91sam9260-dbgu
- const: atmel,at91sam9260-usart - const: atmel,at91sam9260-usart
- items:
- const: microchip,sam9x60-usart
- const: atmel,at91sam9260-usart
- items: - items:
- const: microchip,sam9x60-dbgu - const: microchip,sam9x60-dbgu
- const: microchip,sam9x60-usart - const: microchip,sam9x60-usart

5
Documentation/filesystems/locking.rst
View File

@ -551,9 +551,8 @@ mutex or just to use i_size_read() instead.
Note: this does not protect the file->f_pos against concurrent modifications Note: this does not protect the file->f_pos against concurrent modifications
since this is something the userspace has to take care about. since this is something the userspace has to take care about.
->iterate() is called with i_rwsem exclusive. ->iterate_shared() is called with i_rwsem held for reading, and with the
file f_pos_lock held exclusively
->iterate_shared() is called with i_rwsem at least shared.
->fasync() is responsible for maintaining the FASYNC bit in filp->f_flags. ->fasync() is responsible for maintaining the FASYNC bit in filp->f_flags.
Most instances call fasync_helper(), which does that maintenance, so it's Most instances call fasync_helper(), which does that maintenance, so it's

25
Documentation/filesystems/porting.rst
View File

@ -537,7 +537,7 @@ vfs_readdir() is gone; switch to iterate_dir() instead
**mandatory** **mandatory**
->readdir() is gone now; switch to ->iterate() ->readdir() is gone now; switch to ->iterate_shared()
**mandatory** **mandatory**
@ -693,24 +693,19 @@ parallel now.
--- ---
**recommended** **mandatory**
->iterate_shared() is added; it's a parallel variant of ->iterate(). ->iterate_shared() is added.
Exclusion on struct file level is still provided (as well as that Exclusion on struct file level is still provided (as well as that
between it and lseek on the same struct file), but if your directory between it and lseek on the same struct file), but if your directory
has been opened several times, you can get these called in parallel. has been opened several times, you can get these called in parallel.
Exclusion between that method and all directory-modifying ones is Exclusion between that method and all directory-modifying ones is
still provided, of course. still provided, of course.
Often enough ->iterate() can serve as ->iterate_shared() without any If you have any per-inode or per-dentry in-core data structures modified
changes - it is a read-only operation, after all. If you have any by ->iterate_shared(), you might need something to serialize the access
per-inode or per-dentry in-core data structures modified by ->iterate(), to them. If you do dcache pre-seeding, you'll need to switch to
you might need something to serialize the access to them. If you d_alloc_parallel() for that; look for in-tree examples.
do dcache pre-seeding, you'll need to switch to d_alloc_parallel() for
that; look for in-tree examples.
Old method is only used if the new one is absent; eventually it will
be removed. Switch while you still can; the old one won't stay.
--- ---
@ -930,9 +925,9 @@ should be done by looking at FMODE_LSEEK in file->f_mode.
filldir_t (readdir callbacks) calling conventions have changed. Instead of filldir_t (readdir callbacks) calling conventions have changed. Instead of
returning 0 or -E... it returns bool now. false means "no more" (as -E... used returning 0 or -E... it returns bool now. false means "no more" (as -E... used
to) and true - "keep going" (as 0 in old calling conventions). Rationale: to) and true - "keep going" (as 0 in old calling conventions). Rationale:
callers never looked at specific -E... values anyway. ->iterate() and callers never looked at specific -E... values anyway. -> iterate_shared()
->iterate_shared() instance require no changes at all, all filldir_t ones in instances require no changes at all, all filldir_t ones in the tree
the tree converted. converted.
--- ---

2
Documentation/i2c/writing-clients.rst
View File

@ -46,7 +46,7 @@ driver model device node, and its I2C address.
}, },
.id_table = foo_idtable, .id_table = foo_idtable,
.probe_new = foo_probe, .probe = foo_probe,
.remove = foo_remove, .remove = foo_remove,
/* if device autodetection is needed: */ /* if device autodetection is needed: */
.class = I2C_CLASS_SOMETHING, .class = I2C_CLASS_SOMETHING,

4
Documentation/networking/nf_conntrack-sysctl.rst
View File

@ -178,10 +178,10 @@ nf_conntrack_sctp_timeout_established - INTEGER (seconds)
Default is set to (hb_interval * path_max_retrans + rto_max) Default is set to (hb_interval * path_max_retrans + rto_max)
nf_conntrack_sctp_timeout_shutdown_sent - INTEGER (seconds) nf_conntrack_sctp_timeout_shutdown_sent - INTEGER (seconds)
default 0.3 default 3
nf_conntrack_sctp_timeout_shutdown_recd - INTEGER (seconds) nf_conntrack_sctp_timeout_shutdown_recd - INTEGER (seconds)
default 0.3 default 3
nf_conntrack_sctp_timeout_shutdown_ack_sent - INTEGER (seconds) nf_conntrack_sctp_timeout_shutdown_ack_sent - INTEGER (seconds)
default 3 default 3

100
MAINTAINERS
View File

@ -2339,7 +2339,7 @@ F: drivers/phy/mediatek/
ARM/MICROCHIP (ARM64) SoC support ARM/MICROCHIP (ARM64) SoC support
M: Conor Dooley <conor@kernel.org> M: Conor Dooley <conor@kernel.org>
M: Nicolas Ferre <nicolas.ferre@microchip.com> M: Nicolas Ferre <nicolas.ferre@microchip.com>
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported S: Supported
T: git https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git T: git https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git
@ -2348,7 +2348,7 @@ F: arch/arm64/boot/dts/microchip/
ARM/Microchip (AT91) SoC support ARM/Microchip (AT91) SoC support
M: Nicolas Ferre <nicolas.ferre@microchip.com> M: Nicolas Ferre <nicolas.ferre@microchip.com>
M: Alexandre Belloni <alexandre.belloni@bootlin.com> M: Alexandre Belloni <alexandre.belloni@bootlin.com>
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported S: Supported
W: http://www.linux4sam.org W: http://www.linux4sam.org
@ -3250,7 +3250,7 @@ F: include/uapi/linux/atm*
ATMEL MACB ETHERNET DRIVER ATMEL MACB ETHERNET DRIVER
M: Nicolas Ferre <nicolas.ferre@microchip.com> M: Nicolas Ferre <nicolas.ferre@microchip.com>
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
S: Supported S: Supported
F: drivers/net/ethernet/cadence/ F: drivers/net/ethernet/cadence/
@ -3262,9 +3262,8 @@ F: Documentation/devicetree/bindings/input/atmel,maxtouch.yaml
F: drivers/input/touchscreen/atmel_mxt_ts.c F: drivers/input/touchscreen/atmel_mxt_ts.c
ATMEL WIRELESS DRIVER ATMEL WIRELESS DRIVER
M: Simon Kelley <simon@thekelleys.org.uk>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Maintained S: Orphan
W: http://www.thekelleys.org.uk/atmel W: http://www.thekelleys.org.uk/atmel
W: http://atmelwlandriver.sourceforge.net/ W: http://atmelwlandriver.sourceforge.net/
F: drivers/net/wireless/atmel/atmel* F: drivers/net/wireless/atmel/atmel*
@ -3394,7 +3393,7 @@ F: drivers/media/radio/radio-aztech*
B43 WIRELESS DRIVER B43 WIRELESS DRIVER
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
L: b43-dev@lists.infradead.org L: b43-dev@lists.infradead.org
S: Odd Fixes S: Orphan
W: https://wireless.wiki.kernel.org/en/users/Drivers/b43 W: https://wireless.wiki.kernel.org/en/users/Drivers/b43
F: drivers/net/wireless/broadcom/b43/ F: drivers/net/wireless/broadcom/b43/
@ -5462,8 +5461,7 @@ F: Documentation/devicetree/bindings/net/can/ctu,ctucanfd.yaml
F: drivers/net/can/ctucanfd/ F: drivers/net/can/ctucanfd/
CW1200 WLAN driver CW1200 WLAN driver
M: Solomon Peachy <pizza@shaftnet.org> S: Orphan
S: Maintained
F: drivers/net/wireless/st/cw1200/ F: drivers/net/wireless/st/cw1200/
CX18 VIDEO4LINUX DRIVER CX18 VIDEO4LINUX DRIVER
@ -8814,6 +8812,7 @@ R: Michael Walle <michael@walle.cc>
S: Maintained S: Maintained
F: drivers/gpio/gpio-regmap.c F: drivers/gpio/gpio-regmap.c
F: include/linux/gpio/regmap.h F: include/linux/gpio/regmap.h
K: (devm_)?gpio_regmap_(un)?register
GPIO SUBSYSTEM GPIO SUBSYSTEM
M: Linus Walleij <linus.walleij@linaro.org> M: Linus Walleij <linus.walleij@linaro.org>
@ -9377,7 +9376,6 @@ F: drivers/crypto/hisilicon/sgl.c
F: include/linux/hisi_acc_qm.h F: include/linux/hisi_acc_qm.h
HISILICON ROCE DRIVER HISILICON ROCE DRIVER
M: Haoyue Xu <xuhaoyue1@hisilicon.com>
M: Junxian Huang <huangjunxian6@hisilicon.com> M: Junxian Huang <huangjunxian6@hisilicon.com>
L: linux-rdma@vger.kernel.org L: linux-rdma@vger.kernel.org
S: Maintained S: Maintained
@ -9662,6 +9660,7 @@ F: tools/hv/
HYPERBUS SUPPORT HYPERBUS SUPPORT
M: Vignesh Raghavendra <vigneshr@ti.com> M: Vignesh Raghavendra <vigneshr@ti.com>
R: Tudor Ambarus <tudor.ambarus@linaro.org>
L: linux-mtd@lists.infradead.org L: linux-mtd@lists.infradead.org
S: Supported S: Supported
Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ Q: http://patchwork.ozlabs.org/project/linux-mtd/list/
@ -12481,6 +12480,7 @@ F: net/mctp/
MAPLE TREE MAPLE TREE
M: Liam R. Howlett <Liam.Howlett@oracle.com> M: Liam R. Howlett <Liam.Howlett@oracle.com>
L: maple-tree@lists.infradead.org
L: linux-mm@kvack.org L: linux-mm@kvack.org
S: Supported S: Supported
F: Documentation/core-api/maple_tree.rst F: Documentation/core-api/maple_tree.rst
@ -12592,18 +12592,14 @@ F: Documentation/devicetree/bindings/net/marvell,pp2.yaml
F: drivers/net/ethernet/marvell/mvpp2/ F: drivers/net/ethernet/marvell/mvpp2/
MARVELL MWIFIEX WIRELESS DRIVER MARVELL MWIFIEX WIRELESS DRIVER
M: Amitkumar Karwar <amitkarwar@gmail.com> M: Brian Norris <briannorris@chromium.org>
M: Ganapathi Bhat <ganapathi017@gmail.com>
M: Sharvari Harisangam <sharvari.harisangam@nxp.com>
M: Xinming Hu <huxinming820@gmail.com>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Maintained S: Odd Fixes
F: drivers/net/wireless/marvell/mwifiex/ F: drivers/net/wireless/marvell/mwifiex/
MARVELL MWL8K WIRELESS DRIVER MARVELL MWL8K WIRELESS DRIVER
M: Lennert Buytenhek <buytenh@wantstofly.org>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Odd Fixes S: Orphan
F: drivers/net/wireless/marvell/mwl8k.c F: drivers/net/wireless/marvell/mwl8k.c
MARVELL NAND CONTROLLER DRIVER MARVELL NAND CONTROLLER DRIVER
@ -13791,7 +13787,7 @@ F: Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
F: drivers/spi/spi-at91-usart.c F: drivers/spi/spi-at91-usart.c
MICROCHIP AUDIO ASOC DRIVERS MICROCHIP AUDIO ASOC DRIVERS
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
L: alsa-devel@alsa-project.org (moderated for non-subscribers) L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Supported S: Supported
F: Documentation/devicetree/bindings/sound/atmel* F: Documentation/devicetree/bindings/sound/atmel*
@ -13814,7 +13810,7 @@ S: Maintained
F: drivers/crypto/atmel-ecc.* F: drivers/crypto/atmel-ecc.*
MICROCHIP EIC DRIVER MICROCHIP EIC DRIVER
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported S: Supported
F: Documentation/devicetree/bindings/interrupt-controller/microchip,sama7g5-eic.yaml F: Documentation/devicetree/bindings/interrupt-controller/microchip,sama7g5-eic.yaml
@ -13887,7 +13883,7 @@ F: drivers/video/fbdev/atmel_lcdfb.c
F: include/video/atmel_lcdc.h F: include/video/atmel_lcdc.h
MICROCHIP MCP16502 PMIC DRIVER MICROCHIP MCP16502 PMIC DRIVER
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported S: Supported
F: Documentation/devicetree/bindings/regulator/mcp16502-regulator.txt F: Documentation/devicetree/bindings/regulator/mcp16502-regulator.txt
@ -13914,7 +13910,7 @@ F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
F: drivers/mtd/nand/raw/atmel/* F: drivers/mtd/nand/raw/atmel/*
MICROCHIP OTPC DRIVER MICROCHIP OTPC DRIVER
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported S: Supported
F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
@ -13953,7 +13949,7 @@ F: Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
F: drivers/fpga/microchip-spi.c F: drivers/fpga/microchip-spi.c
MICROCHIP PWM DRIVER MICROCHIP PWM DRIVER
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-pwm@vger.kernel.org L: linux-pwm@vger.kernel.org
S: Supported S: Supported
@ -13969,7 +13965,7 @@ F: drivers/iio/adc/at91-sama5d2_adc.c
F: include/dt-bindings/iio/adc/at91-sama5d2_adc.h F: include/dt-bindings/iio/adc/at91-sama5d2_adc.h
MICROCHIP SAMA5D2-COMPATIBLE SHUTDOWN CONTROLLER MICROCHIP SAMA5D2-COMPATIBLE SHUTDOWN CONTROLLER
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
S: Supported S: Supported
F: Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml F: Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
F: drivers/power/reset/at91-sama5d2_shdwc.c F: drivers/power/reset/at91-sama5d2_shdwc.c
@ -13986,7 +13982,7 @@ S: Supported
F: drivers/spi/spi-atmel.* F: drivers/spi/spi-atmel.*
MICROCHIP SSC DRIVER MICROCHIP SSC DRIVER
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported S: Supported
F: Documentation/devicetree/bindings/misc/atmel-ssc.txt F: Documentation/devicetree/bindings/misc/atmel-ssc.txt
@ -14015,7 +14011,7 @@ F: drivers/usb/gadget/udc/atmel_usba_udc.*
MICROCHIP WILC1000 WIFI DRIVER MICROCHIP WILC1000 WIFI DRIVER
M: Ajay Singh <ajay.kathat@microchip.com> M: Ajay Singh <ajay.kathat@microchip.com>
M: Claudiu Beznea <claudiu.beznea@microchip.com> M: Claudiu Beznea <claudiu.beznea@tuxon.dev>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Supported S: Supported
F: drivers/net/wireless/microchip/wilc1000/ F: drivers/net/wireless/microchip/wilc1000/
@ -16298,6 +16294,7 @@ F: drivers/pci/controller/dwc/pci-exynos.c
PCI DRIVER FOR SYNOPSYS DESIGNWARE PCI DRIVER FOR SYNOPSYS DESIGNWARE
M: Jingoo Han <jingoohan1@gmail.com> M: Jingoo Han <jingoohan1@gmail.com>
M: Gustavo Pimentel <gustavo.pimentel@synopsys.com> M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-pci@vger.kernel.org L: linux-pci@vger.kernel.org
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@ -17449,6 +17446,7 @@ F: drivers/media/tuners/qt1010*
QUALCOMM ATH12K WIRELESS DRIVER QUALCOMM ATH12K WIRELESS DRIVER
M: Kalle Valo <kvalo@kernel.org> M: Kalle Valo <kvalo@kernel.org>
M: Jeff Johnson <quic_jjohnson@quicinc.com>
L: ath12k@lists.infradead.org L: ath12k@lists.infradead.org
S: Supported S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
@ -17456,6 +17454,7 @@ F: drivers/net/wireless/ath/ath12k/
QUALCOMM ATHEROS ATH10K WIRELESS DRIVER QUALCOMM ATHEROS ATH10K WIRELESS DRIVER
M: Kalle Valo <kvalo@kernel.org> M: Kalle Valo <kvalo@kernel.org>
M: Jeff Johnson <quic_jjohnson@quicinc.com>
L: ath10k@lists.infradead.org L: ath10k@lists.infradead.org
S: Supported S: Supported
W: https://wireless.wiki.kernel.org/en/users/Drivers/ath10k W: https://wireless.wiki.kernel.org/en/users/Drivers/ath10k
@ -17465,6 +17464,7 @@ F: drivers/net/wireless/ath/ath10k/
QUALCOMM ATHEROS ATH11K WIRELESS DRIVER QUALCOMM ATHEROS ATH11K WIRELESS DRIVER
M: Kalle Valo <kvalo@kernel.org> M: Kalle Valo <kvalo@kernel.org>
M: Jeff Johnson <quic_jjohnson@quicinc.com>
L: ath11k@lists.infradead.org L: ath11k@lists.infradead.org
S: Supported S: Supported
W: https://wireless.wiki.kernel.org/en/users/Drivers/ath11k W: https://wireless.wiki.kernel.org/en/users/Drivers/ath11k
@ -17985,7 +17985,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.g
F: drivers/net/wireless/realtek/rtlwifi/ F: drivers/net/wireless/realtek/rtlwifi/
REALTEK WIRELESS DRIVER (rtw88) REALTEK WIRELESS DRIVER (rtw88)
M: Yan-Hsuan Chuang <tony0620emma@gmail.com> M: Ping-Ke Shih <pkshih@realtek.com>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Maintained S: Maintained
F: drivers/net/wireless/realtek/rtw88/ F: drivers/net/wireless/realtek/rtw88/
@ -18510,17 +18510,14 @@ RTL8180 WIRELESS DRIVER
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Orphan S: Orphan
W: https://wireless.wiki.kernel.org/ W: https://wireless.wiki.kernel.org/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git
F: drivers/net/wireless/realtek/rtl818x/rtl8180/ F: drivers/net/wireless/realtek/rtl818x/rtl8180/
RTL8187 WIRELESS DRIVER RTL8187 WIRELESS DRIVER
M: Herton Ronaldo Krzesinski <herton@canonical.com> M: Hin-Tak Leung <hintak.leung@gmail.com>
M: Hin-Tak Leung <htl10@users.sourceforge.net>
M: Larry Finger <Larry.Finger@lwfinger.net> M: Larry Finger <Larry.Finger@lwfinger.net>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Maintained S: Maintained
W: https://wireless.wiki.kernel.org/ W: https://wireless.wiki.kernel.org/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git
F: drivers/net/wireless/realtek/rtl818x/rtl8187/ F: drivers/net/wireless/realtek/rtl818x/rtl8187/
RTL8XXXU WIRELESS DRIVER (rtl8xxxu) RTL8XXXU WIRELESS DRIVER (rtl8xxxu)
@ -19227,13 +19224,6 @@ F: Documentation/devicetree/bindings/serial/serial.yaml
F: drivers/tty/serdev/ F: drivers/tty/serdev/
F: include/linux/serdev.h F: include/linux/serdev.h
SERIAL DRIVERS
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
L: linux-serial@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/serial/
F: drivers/tty/serial/
SERIAL IR RECEIVER SERIAL IR RECEIVER
M: Sean Young <sean@mess.org> M: Sean Young <sean@mess.org>
L: linux-media@vger.kernel.org L: linux-media@vger.kernel.org
@ -20404,7 +20394,6 @@ F: drivers/pwm/pwm-stm32*
F: include/linux/*/stm32-*tim* F: include/linux/*/stm32-*tim*
STMMAC ETHERNET DRIVER STMMAC ETHERNET DRIVER
M: Giuseppe Cavallaro <peppe.cavallaro@st.com>
M: Alexandre Torgue <alexandre.torgue@foss.st.com> M: Alexandre Torgue <alexandre.torgue@foss.st.com>
M: Jose Abreu <joabreu@synopsys.com> M: Jose Abreu <joabreu@synopsys.com>
L: netdev@vger.kernel.org L: netdev@vger.kernel.org
@ -21639,20 +21628,16 @@ W: https://github.com/srcres258/linux-doc
T: git git://github.com/srcres258/linux-doc.git doc-zh-tw T: git git://github.com/srcres258/linux-doc.git doc-zh-tw
F: Documentation/translations/zh_TW/ F: Documentation/translations/zh_TW/
TTY LAYER TTY LAYER AND SERIAL DRIVERS
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
M: Jiri Slaby <jirislaby@kernel.org> M: Jiri Slaby <jirislaby@kernel.org>
L: linux-kernel@vger.kernel.org L: linux-kernel@vger.kernel.org
L: linux-serial@vger.kernel.org L: linux-serial@vger.kernel.org
S: Supported S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git
F: Documentation/devicetree/bindings/serial/
F: Documentation/driver-api/serial/ F: Documentation/driver-api/serial/
F: drivers/tty/ F: drivers/tty/
F: drivers/tty/serial/serial_base.h
F: drivers/tty/serial/serial_base_bus.c
F: drivers/tty/serial/serial_core.c
F: drivers/tty/serial/serial_ctrl.c
F: drivers/tty/serial/serial_port.c
F: include/linux/selection.h F: include/linux/selection.h
F: include/linux/serial.h F: include/linux/serial.h
F: include/linux/serial_core.h F: include/linux/serial_core.h
@ -21681,11 +21666,14 @@ S: Orphan
F: drivers/net/ethernet/dec/tulip/ F: drivers/net/ethernet/dec/tulip/
TUN/TAP driver TUN/TAP driver
M: Maxim Krasnyansky <maxk@qti.qualcomm.com> M: Willem de Bruijn <willemdebruijn.kernel@gmail.com>
M: Jason Wang <jasowang@redhat.com>
S: Maintained S: Maintained
W: http://vtun.sourceforge.net/tun W: http://vtun.sourceforge.net/tun
F: Documentation/networking/tuntap.rst F: Documentation/networking/tuntap.rst
F: arch/um/os-Linux/drivers/ F: arch/um/os-Linux/drivers/
F: drivers/net/tap.c
F: drivers/net/tun.c
TURBOCHANNEL SUBSYSTEM TURBOCHANNEL SUBSYSTEM
M: "Maciej W. Rozycki" <macro@orcam.me.uk> M: "Maciej W. Rozycki" <macro@orcam.me.uk>
@ -21908,9 +21896,8 @@ S: Maintained
F: drivers/usb/misc/apple-mfi-fastcharge.c F: drivers/usb/misc/apple-mfi-fastcharge.c
USB AR5523 WIRELESS DRIVER USB AR5523 WIRELESS DRIVER
M: Pontus Fuchs <pontus.fuchs@gmail.com>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Maintained S: Orphan
F: drivers/net/wireless/ath/ar5523/ F: drivers/net/wireless/ath/ar5523/
USB ATTACHED SCSI USB ATTACHED SCSI
@ -22187,9 +22174,8 @@ F: drivers/usb/gadget/legacy/webcam.c
F: include/uapi/linux/usb/g_uvc.h F: include/uapi/linux/usb/g_uvc.h
USB WIRELESS RNDIS DRIVER (rndis_wlan) USB WIRELESS RNDIS DRIVER (rndis_wlan)
M: Jussi Kivilinna <jussi.kivilinna@iki.fi>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Maintained S: Orphan
F: drivers/net/wireless/legacy/rndis_wlan.c F: drivers/net/wireless/legacy/rndis_wlan.c
USB XHCI DRIVER USB XHCI DRIVER
@ -22478,7 +22464,6 @@ L: virtualization@lists.linux-foundation.org
S: Maintained S: Maintained
F: drivers/block/virtio_blk.c F: drivers/block/virtio_blk.c
F: drivers/scsi/virtio_scsi.c F: drivers/scsi/virtio_scsi.c
F: drivers/vhost/scsi.c
F: include/uapi/linux/virtio_blk.h F: include/uapi/linux/virtio_blk.h
F: include/uapi/linux/virtio_scsi.h F: include/uapi/linux/virtio_scsi.h
@ -22577,6 +22562,16 @@ F: include/linux/vhost_iotlb.h
F: include/uapi/linux/vhost.h F: include/uapi/linux/vhost.h
F: kernel/vhost_task.c F: kernel/vhost_task.c
VIRTIO HOST (VHOST-SCSI)
M: "Michael S. Tsirkin" <mst@redhat.com>
M: Jason Wang <jasowang@redhat.com>
M: Mike Christie <michael.christie@oracle.com>
R: Paolo Bonzini <pbonzini@redhat.com>
R: Stefan Hajnoczi <stefanha@redhat.com>
L: virtualization@lists.linux-foundation.org
S: Maintained
F: drivers/vhost/scsi.c
VIRTIO I2C DRIVER VIRTIO I2C DRIVER
M: Conghui Chen <conghui.chen@intel.com> M: Conghui Chen <conghui.chen@intel.com>
M: Viresh Kumar <viresh.kumar@linaro.org> M: Viresh Kumar <viresh.kumar@linaro.org>
@ -22964,7 +22959,7 @@ F: drivers/input/misc/wistron_btns.c
WL3501 WIRELESS PCMCIA CARD DRIVER WL3501 WIRELESS PCMCIA CARD DRIVER
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
S: Odd fixes S: Orphan
F: drivers/net/wireless/legacy/wl3501* F: drivers/net/wireless/legacy/wl3501*
WMI BINARY MOF DRIVER WMI BINARY MOF DRIVER
@ -23535,11 +23530,8 @@ S: Maintained
F: mm/zbud.c F: mm/zbud.c
ZD1211RW WIRELESS DRIVER ZD1211RW WIRELESS DRIVER
M: Ulrich Kunitz <kune@deine-taler.de>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
L: zd1211-devs@lists.sourceforge.net (subscribers-only) S: Orphan
S: Maintained
W: http://zd1211.ath.cx/wiki/DriverRewrite
F: drivers/net/wireless/zydas/zd1211rw/ F: drivers/net/wireless/zydas/zd1211rw/
ZD1301 MEDIA DRIVER ZD1301 MEDIA DRIVER

2
Makefile
View File

@ -2,7 +2,7 @@
VERSION = 6 VERSION = 6
PATCHLEVEL = 5 PATCHLEVEL = 5
SUBLEVEL = 0 SUBLEVEL = 0
EXTRAVERSION = -rc4 EXTRAVERSION = -rc6
NAME = Hurr durr I'ma ninja sloth NAME = Hurr durr I'ma ninja sloth
# *DOCUMENTATION* # *DOCUMENTATION*

13
arch/alpha/include/asm/processor.h
View File

@ -47,12 +47,6 @@ unsigned long __get_wchan(struct task_struct *p);
#define ARCH_HAS_PREFETCH #define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW #define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH
#ifndef CONFIG_SMP
/* Nothing to prefetch. */
#define spin_lock_prefetch(lock) do { } while (0)
#endif
extern inline void prefetch(const void *ptr) extern inline void prefetch(const void *ptr)
{ {
@ -64,11 +58,4 @@ extern inline void prefetchw(const void *ptr)
__builtin_prefetch(ptr, 1, 3); __builtin_prefetch(ptr, 1, 3);
} }
#ifdef CONFIG_SMP
extern inline void spin_lock_prefetch(const void *ptr)
{
__builtin_prefetch(ptr, 1, 3);
}
#endif
#endif /* __ASM_ALPHA_PROCESSOR_H */ #endif /* __ASM_ALPHA_PROCESSOR_H */

3
arch/alpha/kernel/setup.c
View File

@ -385,8 +385,7 @@ setup_memory(void *kernel_end)
#endif /* CONFIG_BLK_DEV_INITRD */ #endif /* CONFIG_BLK_DEV_INITRD */
} }
int __init int page_is_ram(unsigned long pfn)
page_is_ram(unsigned long pfn)
{ {
struct memclust_struct * cluster; struct memclust_struct * cluster;
struct memdesc_struct * memdesc; struct memdesc_struct * memdesc;

2
arch/arm/boot/dts/arm/integratorap.dts
View File

@ -158,7 +158,7 @@
valid-mask = <0x003fffff>; valid-mask = <0x003fffff>;
}; };
pci: pciv3@62000000 { pci: pci@62000000 {
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
device_type = "pci"; device_type = "pci";
#interrupt-cells = <1>; #interrupt-cells = <1>;

26
arch/arm/boot/dts/microchip/sam9x60.dtsi
View File

@ -172,7 +172,7 @@
status = "disabled"; status = "disabled";
uart4: serial@200 { uart4: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -240,7 +240,7 @@
status = "disabled"; status = "disabled";
uart5: serial@200 { uart5: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>; atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
@ -370,7 +370,7 @@
status = "disabled"; status = "disabled";
uart11: serial@200 { uart11: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -419,7 +419,7 @@
status = "disabled"; status = "disabled";
uart12: serial@200 { uart12: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -576,7 +576,7 @@
status = "disabled"; status = "disabled";
uart6: serial@200 { uart6: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -625,7 +625,7 @@
status = "disabled"; status = "disabled";
uart7: serial@200 { uart7: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -674,7 +674,7 @@
status = "disabled"; status = "disabled";
uart8: serial@200 { uart8: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -723,7 +723,7 @@
status = "disabled"; status = "disabled";
uart0: serial@200 { uart0: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -791,7 +791,7 @@
status = "disabled"; status = "disabled";
uart1: serial@200 { uart1: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -859,7 +859,7 @@
status = "disabled"; status = "disabled";
uart2: serial@200 { uart2: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -927,7 +927,7 @@
status = "disabled"; status = "disabled";
uart3: serial@200 { uart3: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -1050,7 +1050,7 @@
status = "disabled"; status = "disabled";
uart9: serial@200 { uart9: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0
@ -1099,7 +1099,7 @@
status = "disabled"; status = "disabled";
uart10: serial@200 { uart10: serial@200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>; reg = <0x200 0x200>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0 dmas = <&dma0

2
arch/arm/boot/dts/nspire/nspire.dtsi
View File

@ -161,7 +161,7 @@
}; };
watchdog: watchdog@90060000 { watchdog: watchdog@90060000 {
compatible = "arm,amba-primecell"; compatible = "arm,primecell";
reg = <0x90060000 0x1000>; reg = <0x90060000 0x1000>;
interrupts = <3>; interrupts = <3>;
}; };

10
arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts
View File

@ -60,6 +60,16 @@
status = "okay"; status = "okay";
}; };
&cpu0 {
/* CPU rated to 800 MHz, not the default 1.2GHz. */
operating-points = <
/* kHz uV */
166666 850000
400000 900000
800000 1050000
>;
};
&ecspi1 { &ecspi1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>; pinctrl-0 = <&pinctrl_ecspi1>;

2
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
View File

@ -182,7 +182,7 @@
pinctrl-0 = <&pinctrl_rtc_int>; pinctrl-0 = <&pinctrl_rtc_int>;
reg = <0x68>; reg = <0x68>;
interrupt-parent = <&gpio7>; interrupt-parent = <&gpio7>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
status = "disabled"; status = "disabled";
}; };
}; };

2
arch/arm/boot/dts/nxp/imx/imx6sll.dtsi
View File

@ -552,7 +552,7 @@
reg = <0x020ca000 0x1000>; reg = <0x020ca000 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_USBPHY2>; clocks = <&clks IMX6SLL_CLK_USBPHY2>;
phy-reg_3p0-supply = <&reg_3p0>; phy-3p0-supply = <&reg_3p0>;
fsl,anatop = <&anatop>; fsl,anatop = <&anatop>;
}; };

14
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
View File

@ -863,7 +863,6 @@
reg = <0>; reg = <0>;
ldb_from_lcdif1: endpoint { ldb_from_lcdif1: endpoint {
remote-endpoint = <&lcdif1_to_ldb>;
}; };
}; };
@ -1010,6 +1009,8 @@
<&clks IMX6SX_CLK_USDHC1>; <&clks IMX6SX_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
bus-width = <4>; bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled"; status = "disabled";
}; };
@ -1022,6 +1023,8 @@
<&clks IMX6SX_CLK_USDHC2>; <&clks IMX6SX_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
bus-width = <4>; bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled"; status = "disabled";
}; };
@ -1034,6 +1037,8 @@
<&clks IMX6SX_CLK_USDHC3>; <&clks IMX6SX_CLK_USDHC3>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
bus-width = <4>; bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled"; status = "disabled";
}; };
@ -1309,11 +1314,8 @@
power-domains = <&pd_disp>; power-domains = <&pd_disp>;
status = "disabled"; status = "disabled";
ports { port {
port { lcdif1_to_ldb: endpoint {
lcdif1_to_ldb: endpoint {
remote-endpoint = <&ldb_from_lcdif1>;
};
}; };
}; };
}; };

6
arch/arm/boot/dts/nxp/imx/imx7s.dtsi
View File

@ -1184,6 +1184,8 @@
<&clks IMX7D_USDHC1_ROOT_CLK>; <&clks IMX7D_USDHC1_ROOT_CLK>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
bus-width = <4>; bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled"; status = "disabled";
}; };
@ -1196,6 +1198,8 @@
<&clks IMX7D_USDHC2_ROOT_CLK>; <&clks IMX7D_USDHC2_ROOT_CLK>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
bus-width = <4>; bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled"; status = "disabled";
}; };
@ -1208,6 +1212,8 @@
<&clks IMX7D_USDHC3_ROOT_CLK>; <&clks IMX7D_USDHC3_ROOT_CLK>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
bus-width = <4>; bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled"; status = "disabled";
}; };

9
arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi
View File

@ -145,6 +145,8 @@
/* MDIO */ /* MDIO */
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
/* Added to support GPIO controlled PHY reset */
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE7)
>; >;
}; };
@ -153,6 +155,8 @@
/* MDIO reset value */ /* MDIO reset value */
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
/* Added to support GPIO controlled PHY reset */
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
>; >;
}; };
@ -215,6 +219,7 @@
baseboard_eeprom: baseboard_eeprom@50 { baseboard_eeprom: baseboard_eeprom@50 {
compatible = "atmel,24c256"; compatible = "atmel,24c256";
reg = <0x50>; reg = <0x50>;
vcc-supply = <&ldo4_reg>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@ -377,6 +382,10 @@
ethphy0: ethernet-phy@0 { ethphy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
/* Support GPIO reset on revision C3 boards */
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <300>;
reset-deassert-us = <6500>;
}; };
}; };

1
arch/arm/mach-pxa/sharpsl_pm.h
View File

@ -105,5 +105,4 @@ void sharpsl_pm_led(int val);
#define MAX1111_ACIN_VOLT 6u #define MAX1111_ACIN_VOLT 6u
int sharpsl_pm_pxa_read_max1111(int channel); int sharpsl_pm_pxa_read_max1111(int channel);
void corgi_lcd_limit_intensity(int limit);
#endif #endif

1
arch/arm/mach-pxa/spitz_pm.c
View File

@ -15,6 +15,7 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/apm-emulation.h> #include <linux/apm-emulation.h>
#include <linux/spi/corgi_lcd.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>

2
arch/arm/mach-zynq/pm.c
View File

@ -8,8 +8,8 @@
*/ */
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_device.h>
#include "common.h" #include "common.h"
/* register offsets */ /* register offsets */

2
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View File

@ -145,7 +145,7 @@
status = "okay"; status = "okay";
clock-frequency = <100000>; clock-frequency = <100000>;
i2c-sda-falling-time-ns = <890>; /* hcnt */ i2c-sda-falling-time-ns = <890>; /* hcnt */
i2c-sdl-falling-time-ns = <890>; /* lcnt */ i2c-scl-falling-time-ns = <890>; /* lcnt */
pinctrl-names = "default", "gpio"; pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c1_pmx_func>; pinctrl-0 = <&i2c1_pmx_func>;

2
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
View File

@ -141,7 +141,7 @@
status = "okay"; status = "okay";
clock-frequency = <100000>; clock-frequency = <100000>;
i2c-sda-falling-time-ns = <890>; /* hcnt */ i2c-sda-falling-time-ns = <890>; /* hcnt */
i2c-sdl-falling-time-ns = <890>; /* lcnt */ i2c-scl-falling-time-ns = <890>; /* lcnt */
adc@14 { adc@14 {
compatible = "lltc,ltc2497"; compatible = "lltc,ltc2497";

1
arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi
View File

@ -1 +0,0 @@
../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi

2
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
View File

@ -141,7 +141,7 @@
}; };
&gpio1 { &gpio1 {
gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY", "", "", "", "RESET_ETHPHY",
"CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
"USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";

4
arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
View File

@ -111,7 +111,7 @@
}; };
&gpio1 { &gpio1 {
gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", gpio-line-names = "", "", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY", "", "", "", "RESET_ETHPHY",
"", "", "nENABLE_FLATLINK"; "", "", "nENABLE_FLATLINK";
}; };
@ -210,7 +210,7 @@
}; };
}; };
reg_vdd_gpu: buck3 { reg_vdd_vpu: buck3 {
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-max-microvolt = <1000000>; regulator-max-microvolt = <1000000>;

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
View File

@ -567,6 +567,10 @@
status = "okay"; status = "okay";
}; };
&disp_blk_ctrl {
status = "disabled";
};
&pgc_mipi { &pgc_mipi {
status = "disabled"; status = "disabled";
}; };

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
View File

@ -628,6 +628,10 @@
status = "okay"; status = "okay";
}; };
&disp_blk_ctrl {
status = "disabled";
};
&pgc_mipi { &pgc_mipi {
status = "disabled"; status = "disabled";
}; };

7
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -1221,10 +1221,9 @@
compatible = "fsl,imx8mm-mipi-csi2"; compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>; reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
<&clk IMX8MM_CLK_CSI1_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL2_1000M>;
clock-frequency = <333000000>; clock-frequency = <333000000>;
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_CSI1_ROOT>, <&clk IMX8MM_CLK_CSI1_ROOT>,

2
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
View File

@ -358,7 +358,7 @@
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x159
>; >;
}; };

6
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -1175,10 +1175,8 @@
compatible = "fsl,imx8mm-mipi-csi2"; compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>; reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
<&clk IMX8MN_CLK_CSI1_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL2_1000M>;
assigned-clock-rates = <333000000>; assigned-clock-rates = <333000000>;
clock-frequency = <333000000>; clock-frequency = <333000000>;
clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,

2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -772,7 +772,7 @@
<&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_VPU_PLL>; <&clk IMX8MQ_VPU_PLL>;
assigned-clock-rates = <600000000>, assigned-clock-rates = <600000000>,
<600000000>, <300000000>,
<800000000>, <800000000>,
<0>; <0>;
}; };

2
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@ -340,7 +340,7 @@
anatop: anatop@44480000 { anatop: anatop@44480000 {
compatible = "fsl,imx93-anatop", "syscon"; compatible = "fsl,imx93-anatop", "syscon";
reg = <0x44480000 0x10000>; reg = <0x44480000 0x2000>;
}; };
adc1: adc@44530000 { adc1: adc@44530000 {

2
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View File

@ -121,7 +121,7 @@
}; };
}; };
pm8150l-thermal { pm8150l-pcb-thermal {
polling-delay-passive = <0>; polling-delay-passive = <0>;
polling-delay = <0>; polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 1>; thermal-sensors = <&pm8150l_adc_tm 1>;

4
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
View File

@ -153,8 +153,8 @@
vreg_l4c: ldo4 { vreg_l4c: ldo4 {
regulator-name = "vreg_l4c"; regulator-name = "vreg_l4c";
regulator-min-microvolt = <1100000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>; regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
/* /*
* FIXME: This should have regulator-allow-set-load but * FIXME: This should have regulator-allow-set-load but

4
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -3120,8 +3120,8 @@
reg = <0 0x0ae94400 0 0x200>, reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>, <0 0x0ae94600 0 0x280>,
<0 0x0ae94a00 0 0x1e0>; <0 0x0ae94a00 0 0x1e0>;
reg-names = "dsi0_phy", reg-names = "dsi_phy",
"dsi0_phy_lane", "dsi_phy_lane",
"dsi_pll"; "dsi_pll";
#clock-cells = <1>; #clock-cells = <1>;

2
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -3561,7 +3561,7 @@
}; };
osm_l3: interconnect@18321000 { osm_l3: interconnect@18321000 {
compatible = "qcom,sc8180x-osm-l3"; compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
reg = <0 0x18321000 0 0x1400>; reg = <0 0x18321000 0 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

18
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -56,7 +56,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD0>; power-domains = <&CPU_PD0>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
@ -85,7 +85,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD1>; power-domains = <&CPU_PD1>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
@ -109,7 +109,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD2>; power-domains = <&CPU_PD2>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
@ -133,7 +133,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD3>; power-domains = <&CPU_PD3>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
@ -157,7 +157,7 @@
qcom,freq-domain = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>; operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD4>; power-domains = <&CPU_PD4>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
@ -181,7 +181,7 @@
qcom,freq-domain = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>; operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD5>; power-domains = <&CPU_PD5>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
@ -205,7 +205,7 @@
qcom,freq-domain = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>; operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD6>; power-domains = <&CPU_PD6>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
@ -229,7 +229,7 @@
qcom,freq-domain = <&cpufreq_hw 2>; qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu7_opp_table>; operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD7>; power-domains = <&CPU_PD7>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
@ -4342,7 +4342,7 @@
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate"; clock-names = "xo", "alternate";
#interconnect-cells = <2>; #interconnect-cells = <1>;
}; };
cpufreq_hw: cpufreq@18323000 { cpufreq_hw: cpufreq@18323000 {

18
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -107,7 +107,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_0: l2-cache { L2_0: l2-cache {
compatible = "cache"; compatible = "cache";
@ -138,7 +138,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_100: l2-cache { L2_100: l2-cache {
compatible = "cache"; compatible = "cache";
@ -163,7 +163,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_200: l2-cache { L2_200: l2-cache {
compatible = "cache"; compatible = "cache";
@ -188,7 +188,7 @@
qcom,freq-domain = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_300: l2-cache { L2_300: l2-cache {
compatible = "cache"; compatible = "cache";
@ -213,7 +213,7 @@
qcom,freq-domain = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>; operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_400: l2-cache { L2_400: l2-cache {
compatible = "cache"; compatible = "cache";
@ -238,7 +238,7 @@
qcom,freq-domain = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>; operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_500: l2-cache { L2_500: l2-cache {
compatible = "cache"; compatible = "cache";
@ -263,7 +263,7 @@
qcom,freq-domain = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>; operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_600: l2-cache { L2_600: l2-cache {
compatible = "cache"; compatible = "cache";
@ -288,7 +288,7 @@
qcom,freq-domain = <&cpufreq_hw 2>; qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu7_opp_table>; operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_700: l2-cache { L2_700: l2-cache {
compatible = "cache"; compatible = "cache";
@ -5679,7 +5679,7 @@
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate"; clock-names = "xo", "alternate";
#interconnect-cells = <2>; #interconnect-cells = <1>;
}; };
cpufreq_hw: cpufreq@18591000 { cpufreq_hw: cpufreq@18591000 {

4
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -1744,6 +1744,8 @@
qcom,controlled-remotely; qcom,controlled-remotely;
iommus = <&apps_smmu 0x594 0x0011>, iommus = <&apps_smmu 0x594 0x0011>,
<&apps_smmu 0x596 0x0011>; <&apps_smmu 0x596 0x0011>;
/* FIXME: Probing BAM DMA causes some abort and system hang */
status = "fail";
}; };
crypto: crypto@1dfa000 { crypto: crypto@1dfa000 {
@ -1755,6 +1757,8 @@
<&apps_smmu 0x596 0x0011>; <&apps_smmu 0x596 0x0011>;
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "memory"; interconnect-names = "memory";
/* FIXME: dependency BAM DMA is disabled */
status = "disabled";
}; };
ipa: ipa@1e40000 { ipa: ipa@1e40000 {

16
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -223,20 +223,20 @@
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tgiv0", "tgie0", "tgif0", "tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tgiv1", "tgiu1", "tgia1", "tgib1", "tciv1", "tciu1",
"tgia2", "tgib2", "tgiv2", "tgiu2", "tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3", "tgia3", "tgib3", "tgic3", "tgid3",
"tgiv3", "tciv3",
"tgia4", "tgib4", "tgic4", "tgid4", "tgia4", "tgib4", "tgic4", "tgid4",
"tgiv4", "tciv4",
"tgiu5", "tgiv5", "tgiw5", "tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6", "tgia6", "tgib6", "tgic6", "tgid6",
"tgiv6", "tciv6",
"tgia7", "tgib7", "tgic7", "tgid7", "tgia7", "tgib7", "tgic7", "tgid7",
"tgiv7", "tciv7",
"tgia8", "tgib8", "tgic8", "tgid8", "tgia8", "tgib8", "tgic8", "tgid8",
"tgiv8", "tgiu8"; "tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>; power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;

16
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -223,20 +223,20 @@
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tgiv0", "tgie0", "tgif0", "tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tgiv1", "tgiu1", "tgia1", "tgib1", "tciv1", "tciu1",
"tgia2", "tgib2", "tgiv2", "tgiu2", "tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3", "tgia3", "tgib3", "tgic3", "tgid3",
"tgiv3", "tciv3",
"tgia4", "tgib4", "tgic4", "tgid4", "tgia4", "tgib4", "tgic4", "tgid4",
"tgiv4", "tciv4",
"tgiu5", "tgiv5", "tgiw5", "tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6", "tgia6", "tgib6", "tgic6", "tgid6",
"tgiv6", "tciv6",
"tgia7", "tgib7", "tgic7", "tgid7", "tgia7", "tgib7", "tgic7", "tgid7",
"tgiv7", "tciv7",
"tgia8", "tgib8", "tgic8", "tgid8", "tgia8", "tgib8", "tgic8", "tgid8",
"tgiv8", "tgiu8"; "tciv8", "tciu8";
clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>; clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
power-domains = <&cpg>; power-domains = <&cpg>;
resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>; resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;

16
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@ -291,14 +291,14 @@
}; };
power-domain@PX30_PD_MMC_NAND { power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>; reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>, clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>, <&cru HCLK_EMMC>,
<&cru HCLK_SDIO>, <&cru HCLK_SDIO>,
<&cru HCLK_SFC>, <&cru HCLK_SFC>,
<&cru SCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_NANDC>, <&cru SCLK_NANDC>,
<&cru SCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SFC>; <&cru SCLK_SFC>;
pm_qos = <&qos_emmc>, <&qos_nand>, pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>; <&qos_sdio>, <&qos_sfc>;
#power-domain-cells = <0>; #power-domain-cells = <0>;

1
arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
View File

@ -106,7 +106,6 @@
regulator-name = "vdd_core"; regulator-name = "vdd_core";
regulator-min-microvolt = <827000>; regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>; regulator-max-microvolt = <1340000>;
regulator-init-microvolt = <1015000>;
regulator-settling-time-up-us = <250>; regulator-settling-time-up-us = <250>;
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;

1
arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
View File

@ -105,7 +105,6 @@
regulator-name = "vdd_core"; regulator-name = "vdd_core";
regulator-min-microvolt = <827000>; regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>; regulator-max-microvolt = <1340000>;
regulator-init-microvolt = <1015000>;
regulator-settling-time-up-us = <250>; regulator-settling-time-up-us = <250>;
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;

2
arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts
View File

@ -773,7 +773,7 @@
compatible = "brcm,bcm4329-fmac"; compatible = "brcm,bcm4329-fmac";
reg = <1>; reg = <1>;
interrupt-parent = <&gpio0>; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake"; interrupt-names = "host-wake";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>; pinctrl-0 = <&wifi_host_wake_l>;

1
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
View File

@ -375,7 +375,6 @@
vcc_sdio: LDO_REG4 { vcc_sdio: LDO_REG4 {
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-init-microvolt = <3000000>;
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sdio"; regulator-name = "vcc_sdio";

3
arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
View File

@ -548,9 +548,8 @@
&sdhci { &sdhci {
max-frequency = <150000000>; max-frequency = <150000000>;
bus-width = <8>; bus-width = <8>;
mmc-hs400-1_8v; mmc-hs200-1_8v;
non-removable; non-removable;
mmc-hs400-enhanced-strobe;
status = "okay"; status = "okay";
}; };

6
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
View File

@ -45,7 +45,7 @@
sdio_pwrseq: sdio-pwrseq { sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple"; compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>; clocks = <&rk808 1>;
clock-names = "ext_clock"; clock-names = "lpo";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>; pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
@ -645,9 +645,9 @@
}; };
&sdhci { &sdhci {
max-frequency = <150000000>;
bus-width = <8>; bus-width = <8>;
mmc-hs400-1_8v; mmc-hs200-1_8v;
mmc-hs400-enhanced-strobe;
non-removable; non-removable;
status = "okay"; status = "okay";
}; };

2
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts
View File

@ -31,7 +31,7 @@
compatible = "brcm,bcm4329-fmac"; compatible = "brcm,bcm4329-fmac";
reg = <1>; reg = <1>;
interrupt-parent = <&gpio0>; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake"; interrupt-names = "host-wake";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>; pinctrl-0 = <&wifi_host_wake_l>;

3
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
View File

@ -356,7 +356,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic"; regulator-name = "vdd_logic";
@ -371,7 +370,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";
@ -533,7 +531,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <712500>; regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>; regulator-max-microvolt = <1390000>;
regulator-init-microvolt = <900000>;
regulator-name = "vdd_cpu"; regulator-name = "vdd_cpu";
regulator-ramp-delay = <2300>; regulator-ramp-delay = <2300>;
vin-supply = <&vcc_sys>; vin-supply = <&vcc_sys>;

4
arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
View File

@ -239,7 +239,7 @@
&gmac1 { &gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
phy-mode = "rgmii"; phy-mode = "rgmii";
clock_in_out = "input"; clock_in_out = "input";
pinctrl-names = "default"; pinctrl-names = "default";
@ -416,7 +416,7 @@
compatible = "brcm,bcm4329-fmac"; compatible = "brcm,bcm4329-fmac";
reg = <1>; reg = <1>;
interrupt-parent = <&gpio2>; interrupt-parent = <&gpio2>;
interrupts = <RK_PB2 GPIO_ACTIVE_HIGH>; interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake"; interrupt-names = "host-wake";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_h>; pinctrl-0 = <&wifi_host_wake_h>;

3
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
View File

@ -218,7 +218,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
@ -233,7 +232,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
@ -259,7 +257,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;

2
arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
View File

@ -264,7 +264,6 @@
regulator-always-on; regulator-always-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
@ -278,7 +277,6 @@
regulator-name = "vdd_gpu_npu"; regulator-name = "vdd_gpu_npu";
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;

2
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
View File

@ -366,7 +366,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic"; regulator-name = "vdd_logic";
@ -381,7 +380,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";

2
arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
View File

@ -277,7 +277,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-state-mem { regulator-state-mem {
@ -292,7 +291,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-state-mem { regulator-state-mem {

4
arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
View File

@ -137,8 +137,8 @@
&mdio1 { &mdio1 {
rgmii_phy1: ethernet-phy@0 { rgmii_phy1: ethernet-phy@0 {
compatible="ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg= <0x0>; reg = <0x0>;
}; };
}; };

2
arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
View File

@ -278,7 +278,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-state-mem { regulator-state-mem {
@ -291,7 +290,6 @@
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-state-mem { regulator-state-mem {

3
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
View File

@ -234,7 +234,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-state-mem { regulator-state-mem {
@ -249,7 +248,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-state-mem { regulator-state-mem {
@ -272,7 +270,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-name = "vdd_npu"; regulator-name = "vdd_npu";
regulator-state-mem { regulator-state-mem {

3
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
View File

@ -308,7 +308,6 @@
regulator-name = "vdd_logic"; regulator-name = "vdd_logic";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -322,7 +321,6 @@
vdd_gpu: DCDC_REG2 { vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";
regulator-always-on; regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -346,7 +344,6 @@
vdd_npu: DCDC_REG4 { vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu"; regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;

3
arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
View File

@ -293,7 +293,6 @@
regulator-name = "vdd_logic"; regulator-name = "vdd_logic";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -307,7 +306,6 @@
vdd_gpu: DCDC_REG2 { vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";
regulator-always-on; regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -331,7 +329,6 @@
vdd_npu: DCDC_REG4 { vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu"; regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;

4
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
View File

@ -173,7 +173,6 @@
regulator-name = "vdd_logic"; regulator-name = "vdd_logic";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -187,7 +186,6 @@
vdd_gpu: DCDC_REG2 { vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";
regulator-always-on; regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -211,7 +209,6 @@
vdd_npu: DCDC_REG4 { vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu"; regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -330,7 +327,6 @@
vcca1v8_image: LDO_REG9 { vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image"; regulator-name = "vcca1v8_image";
regulator-init-microvolt = <950000>;
regulator-min-microvolt = <950000>; regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;

3
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
View File

@ -243,7 +243,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
@ -258,7 +257,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
@ -284,7 +282,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>; regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;

3
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
View File

@ -232,7 +232,6 @@
regulator-name = "vdd_logic"; regulator-name = "vdd_logic";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -246,7 +245,6 @@
vdd_gpu: DCDC_REG2 { vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";
regulator-always-on; regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -270,7 +268,6 @@
vdd_npu: DCDC_REG4 { vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu"; regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;

3
arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
View File

@ -291,7 +291,6 @@
regulator-name = "vdd_logic"; regulator-name = "vdd_logic";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -305,7 +304,6 @@
vdd_gpu: DCDC_REG2 { vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";
regulator-always-on; regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -329,7 +327,6 @@
vdd_npu: DCDC_REG4 { vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu"; regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;

3
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
View File

@ -163,7 +163,6 @@
regulator-name = "vdd_logic"; regulator-name = "vdd_logic";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -177,7 +176,6 @@
vdd_gpu: DCDC_REG2 { vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";
regulator-always-on; regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -201,7 +199,6 @@
vdd_npu: DCDC_REG4 { vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu"; regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;

3
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
View File

@ -350,7 +350,6 @@
regulator-name = "vdd_logic"; regulator-name = "vdd_logic";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -364,7 +363,6 @@
vdd_gpu: DCDC_REG2 { vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu"; regulator-name = "vdd_gpu";
regulator-always-on; regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;
@ -388,7 +386,6 @@
vdd_npu: DCDC_REG4 { vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu"; regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>; regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1350000>;

1
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
View File

@ -337,7 +337,6 @@
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <550000>; regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>; regulator-max-microvolt = <950000>;
regulator-init-microvolt = <750000>;
regulator-ramp-delay = <12500>; regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0"; regulator-name = "vdd_vdenc_s0";

8
arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
View File

@ -125,19 +125,19 @@
cpu-supply = <&vdd_cpu_lit_s0>; cpu-supply = <&vdd_cpu_lit_s0>;
}; };
&cpu_b0{ &cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>; cpu-supply = <&vdd_cpu_big0_s0>;
}; };
&cpu_b1{ &cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>; cpu-supply = <&vdd_cpu_big0_s0>;
}; };
&cpu_b2{ &cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>; cpu-supply = <&vdd_cpu_big1_s0>;
}; };
&cpu_b3{ &cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>; cpu-supply = <&vdd_cpu_big1_s0>;
}; };

44
arch/arm64/include/asm/el2_setup.h
View File

@ -31,6 +31,13 @@
.Lskip_hcrx_\@: .Lskip_hcrx_\@:
.endm .endm
/* Check if running in host at EL2 mode, i.e., (h)VHE. Jump to fail if not. */
.macro __check_hvhe fail, tmp
mrs \tmp, hcr_el2
and \tmp, \tmp, #HCR_E2H
cbz \tmp, \fail
.endm
/* /*
* Allow Non-secure EL1 and EL0 to access physical timer and counter. * Allow Non-secure EL1 and EL0 to access physical timer and counter.
* This is not necessary for VHE, since the host kernel runs in EL2, * This is not necessary for VHE, since the host kernel runs in EL2,
@ -43,9 +50,7 @@
*/ */
.macro __init_el2_timers .macro __init_el2_timers
mov x0, #3 // Enable EL1 physical timers mov x0, #3 // Enable EL1 physical timers
mrs x1, hcr_el2 __check_hvhe .LnVHE_\@, x1
and x1, x1, #HCR_E2H
cbz x1, .LnVHE_\@
lsl x0, x0, #10 lsl x0, x0, #10
.LnVHE_\@: .LnVHE_\@:
msr cnthctl_el2, x0 msr cnthctl_el2, x0
@ -139,15 +144,14 @@
/* Coprocessor traps */ /* Coprocessor traps */
.macro __init_el2_cptr .macro __init_el2_cptr
mrs x1, hcr_el2 __check_hvhe .LnVHE_\@, x1
and x1, x1, #HCR_E2H
cbz x1, .LnVHE_\@
mov x0, #(CPACR_EL1_FPEN_EL1EN | CPACR_EL1_FPEN_EL0EN) mov x0, #(CPACR_EL1_FPEN_EL1EN | CPACR_EL1_FPEN_EL0EN)
b .Lset_cptr_\@ msr cpacr_el1, x0
b .Lskip_set_cptr_\@
.LnVHE_\@: .LnVHE_\@:
mov x0, #0x33ff mov x0, #0x33ff
.Lset_cptr_\@:
msr cptr_el2, x0 // Disable copro. traps to EL2 msr cptr_el2, x0 // Disable copro. traps to EL2
.Lskip_set_cptr_\@:
.endm .endm
/* Disable any fine grained traps */ /* Disable any fine grained traps */
@ -268,19 +272,19 @@
check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2
.Linit_sve_\@: /* SVE register access */ .Linit_sve_\@: /* SVE register access */
mrs x0, cptr_el2 // Disable SVE traps __check_hvhe .Lcptr_nvhe_\@, x1
mrs x1, hcr_el2
and x1, x1, #HCR_E2H
cbz x1, .Lcptr_nvhe_\@
// VHE case // (h)VHE case
mrs x0, cpacr_el1 // Disable SVE traps
orr x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) orr x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
b .Lset_cptr_\@ msr cpacr_el1, x0
b .Lskip_set_cptr_\@
.Lcptr_nvhe_\@: // nVHE case .Lcptr_nvhe_\@: // nVHE case
mrs x0, cptr_el2 // Disable SVE traps
bic x0, x0, #CPTR_EL2_TZ bic x0, x0, #CPTR_EL2_TZ
.Lset_cptr_\@:
msr cptr_el2, x0 msr cptr_el2, x0
.Lskip_set_cptr_\@:
isb isb
mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
msr_s SYS_ZCR_EL2, x1 // length for EL1. msr_s SYS_ZCR_EL2, x1 // length for EL1.
@ -289,9 +293,19 @@
check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2
.Linit_sme_\@: /* SME register access and priority mapping */ .Linit_sme_\@: /* SME register access and priority mapping */
__check_hvhe .Lcptr_nvhe_sme_\@, x1
// (h)VHE case
mrs x0, cpacr_el1 // Disable SME traps
orr x0, x0, #(CPACR_EL1_SMEN_EL0EN | CPACR_EL1_SMEN_EL1EN)
msr cpacr_el1, x0
b .Lskip_set_cptr_sme_\@
.Lcptr_nvhe_sme_\@: // nVHE case
mrs x0, cptr_el2 // Disable SME traps mrs x0, cptr_el2 // Disable SME traps
bic x0, x0, #CPTR_EL2_TSM bic x0, x0, #CPTR_EL2_TSM
msr cptr_el2, x0 msr cptr_el2, x0
.Lskip_set_cptr_sme_\@:
isb isb
mrs x1, sctlr_el2 mrs x1, sctlr_el2

4
arch/arm64/include/asm/fpsimd.h
View File

@ -356,7 +356,7 @@ static inline int sme_max_virtualisable_vl(void)
return vec_max_virtualisable_vl(ARM64_VEC_SME); return vec_max_virtualisable_vl(ARM64_VEC_SME);
} }
extern void sme_alloc(struct task_struct *task); extern void sme_alloc(struct task_struct *task, bool flush);
extern unsigned int sme_get_vl(void); extern unsigned int sme_get_vl(void);
extern int sme_set_current_vl(unsigned long arg); extern int sme_set_current_vl(unsigned long arg);
extern int sme_get_current_vl(void); extern int sme_get_current_vl(void);
@ -388,7 +388,7 @@ static inline void sme_smstart_sm(void) { }
static inline void sme_smstop_sm(void) { } static inline void sme_smstop_sm(void) { }
static inline void sme_smstop(void) { } static inline void sme_smstop(void) { }
static inline void sme_alloc(struct task_struct *task) { } static inline void sme_alloc(struct task_struct *task, bool flush) { }
static inline void sme_setup(void) { } static inline void sme_setup(void) { }
static inline unsigned int sme_get_vl(void) { return 0; } static inline unsigned int sme_get_vl(void) { return 0; }
static inline int sme_max_vl(void) { return 0; } static inline int sme_max_vl(void) { return 0; }

2
arch/arm64/include/asm/kvm_asm.h
View File

@ -278,7 +278,7 @@ asmlinkage void __noreturn hyp_panic_bad_stack(void);
asmlinkage void kvm_unexpected_el2_exception(void); asmlinkage void kvm_unexpected_el2_exception(void);
struct kvm_cpu_context; struct kvm_cpu_context;
void handle_trap(struct kvm_cpu_context *host_ctxt); void handle_trap(struct kvm_cpu_context *host_ctxt);
asmlinkage void __noreturn kvm_host_psci_cpu_entry(bool is_cpu_on); asmlinkage void __noreturn __kvm_host_psci_cpu_entry(bool is_cpu_on);
void __noreturn __pkvm_init_finalise(void); void __noreturn __pkvm_init_finalise(void);
void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc); void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc);
void kvm_patch_vector_branch(struct alt_instr *alt, void kvm_patch_vector_branch(struct alt_instr *alt,

21
arch/arm64/include/asm/kvm_emulate.h
View File

@ -571,6 +571,14 @@ static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature)
return test_bit(feature, vcpu->arch.features); return test_bit(feature, vcpu->arch.features);
} }
static __always_inline void kvm_write_cptr_el2(u64 val)
{
if (has_vhe() || has_hvhe())
write_sysreg(val, cpacr_el1);
else
write_sysreg(val, cptr_el2);
}
static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu) static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu)
{ {
u64 val; u64 val;
@ -578,8 +586,16 @@ static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu)
if (has_vhe()) { if (has_vhe()) {
val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN | val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |
CPACR_EL1_ZEN_EL1EN); CPACR_EL1_ZEN_EL1EN);
if (cpus_have_final_cap(ARM64_SME))
val |= CPACR_EL1_SMEN_EL1EN;
} else if (has_hvhe()) { } else if (has_hvhe()) {
val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN); val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
if (!vcpu_has_sve(vcpu) ||
(vcpu->arch.fp_state != FP_STATE_GUEST_OWNED))
val |= CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN;
if (cpus_have_final_cap(ARM64_SME))
val |= CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN;
} else { } else {
val = CPTR_NVHE_EL2_RES1; val = CPTR_NVHE_EL2_RES1;
@ -597,9 +613,6 @@ static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu)
{ {
u64 val = kvm_get_reset_cptr_el2(vcpu); u64 val = kvm_get_reset_cptr_el2(vcpu);
if (has_vhe() || has_hvhe()) kvm_write_cptr_el2(val);
write_sysreg(val, cpacr_el1);
else
write_sysreg(val, cptr_el2);
} }
#endif /* __ARM64_KVM_EMULATE_H__ */ #endif /* __ARM64_KVM_EMULATE_H__ */

8
arch/arm64/include/asm/processor.h
View File

@ -359,14 +359,6 @@ static inline void prefetchw(const void *ptr)
asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr)); asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
} }
#define ARCH_HAS_SPINLOCK_PREFETCH
static inline void spin_lock_prefetch(const void *ptr)
{
asm volatile(ARM64_LSE_ATOMIC_INSN(
"prfm pstl1strm, %a0",
"nop") : : "p" (ptr));
}
extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */ extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
extern void __init minsigstksz_setup(void); extern void __init minsigstksz_setup(void);

24
arch/arm64/include/uapi/asm/bitsperlong.h Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright (C) 2012 ARM Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ASM_BITSPERLONG_H
#define __ASM_BITSPERLONG_H
#define __BITS_PER_LONG 64
#include <asm-generic/bitsperlong.h>
#endif /* __ASM_BITSPERLONG_H */

15
arch/arm64/kernel/fpsimd.c
View File

@ -679,7 +679,7 @@ static void fpsimd_to_sve(struct task_struct *task)
void *sst = task->thread.sve_state; void *sst = task->thread.sve_state;
struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
if (!system_supports_sve()) if (!system_supports_sve() && !system_supports_sme())
return; return;
vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread)); vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
@ -705,7 +705,7 @@ static void sve_to_fpsimd(struct task_struct *task)
unsigned int i; unsigned int i;
__uint128_t const *p; __uint128_t const *p;
if (!system_supports_sve()) if (!system_supports_sve() && !system_supports_sme())
return; return;
vl = thread_get_cur_vl(&task->thread); vl = thread_get_cur_vl(&task->thread);
@ -835,7 +835,8 @@ void sve_sync_from_fpsimd_zeropad(struct task_struct *task)
void *sst = task->thread.sve_state; void *sst = task->thread.sve_state;
struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
if (!test_tsk_thread_flag(task, TIF_SVE)) if (!test_tsk_thread_flag(task, TIF_SVE) &&
!thread_sm_enabled(&task->thread))
return; return;
vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread)); vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
@ -909,7 +910,7 @@ int vec_set_vector_length(struct task_struct *task, enum vec_type type,
*/ */
task->thread.svcr &= ~(SVCR_SM_MASK | task->thread.svcr &= ~(SVCR_SM_MASK |
SVCR_ZA_MASK); SVCR_ZA_MASK);
clear_thread_flag(TIF_SME); clear_tsk_thread_flag(task, TIF_SME);
free_sme = true; free_sme = true;
} }
} }
@ -1284,9 +1285,9 @@ void fpsimd_release_task(struct task_struct *dead_task)
* the interest of testability and predictability, the architecture * the interest of testability and predictability, the architecture
* guarantees that when ZA is enabled it will be zeroed. * guarantees that when ZA is enabled it will be zeroed.
*/ */
void sme_alloc(struct task_struct *task) void sme_alloc(struct task_struct *task, bool flush)
{ {
if (task->thread.sme_state) { if (task->thread.sme_state && flush) {
memset(task->thread.sme_state, 0, sme_state_size(task)); memset(task->thread.sme_state, 0, sme_state_size(task));
return; return;
} }
@ -1514,7 +1515,7 @@ void do_sme_acc(unsigned long esr, struct pt_regs *regs)
} }
sve_alloc(current, false); sve_alloc(current, false);
sme_alloc(current); sme_alloc(current, true);
if (!current->thread.sve_state || !current->thread.sme_state) { if (!current->thread.sve_state || !current->thread.sme_state) {
force_sig(SIGKILL); force_sig(SIGKILL);
return; return;

30
arch/arm64/kernel/ptrace.c
View File

@ -881,6 +881,13 @@ static int sve_set_common(struct task_struct *target,
break; break;
case ARM64_VEC_SME: case ARM64_VEC_SME:
target->thread.svcr |= SVCR_SM_MASK; target->thread.svcr |= SVCR_SM_MASK;
/*
* Disable traps and ensure there is SME storage but
* preserve any currently set values in ZA/ZT.
*/
sme_alloc(target, false);
set_tsk_thread_flag(target, TIF_SME);
break; break;
default: default:
WARN_ON_ONCE(1); WARN_ON_ONCE(1);
@ -932,11 +939,13 @@ static int sve_set_common(struct task_struct *target,
/* /*
* Ensure target->thread.sve_state is up to date with target's * Ensure target->thread.sve_state is up to date with target's
* FPSIMD regs, so that a short copyin leaves trailing * FPSIMD regs, so that a short copyin leaves trailing
* registers unmodified. Always enable SVE even if going into * registers unmodified. Only enable SVE if we are
* streaming mode. * configuring normal SVE, a system with streaming SVE may not
* have normal SVE.
*/ */
fpsimd_sync_to_sve(target); fpsimd_sync_to_sve(target);
set_tsk_thread_flag(target, TIF_SVE); if (type == ARM64_VEC_SVE)
set_tsk_thread_flag(target, TIF_SVE);
target->thread.fp_type = FP_STATE_SVE; target->thread.fp_type = FP_STATE_SVE;
BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header)); BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header));
@ -1098,7 +1107,7 @@ static int za_set(struct task_struct *target,
} }
/* Allocate/reinit ZA storage */ /* Allocate/reinit ZA storage */
sme_alloc(target); sme_alloc(target, true);
if (!target->thread.sme_state) { if (!target->thread.sme_state) {
ret = -ENOMEM; ret = -ENOMEM;
goto out; goto out;
@ -1168,8 +1177,13 @@ static int zt_set(struct task_struct *target,
if (!system_supports_sme2()) if (!system_supports_sme2())
return -EINVAL; return -EINVAL;
/* Ensure SVE storage in case this is first use of SME */
sve_alloc(target, false);
if (!target->thread.sve_state)
return -ENOMEM;
if (!thread_za_enabled(&target->thread)) { if (!thread_za_enabled(&target->thread)) {
sme_alloc(target); sme_alloc(target, true);
if (!target->thread.sme_state) if (!target->thread.sme_state)
return -ENOMEM; return -ENOMEM;
} }
@ -1177,8 +1191,12 @@ static int zt_set(struct task_struct *target,
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
thread_zt_state(&target->thread), thread_zt_state(&target->thread),
0, ZT_SIG_REG_BYTES); 0, ZT_SIG_REG_BYTES);
if (ret == 0) if (ret == 0) {
target->thread.svcr |= SVCR_ZA_MASK; target->thread.svcr |= SVCR_ZA_MASK;
set_tsk_thread_flag(target, TIF_SME);
}
fpsimd_flush_task_state(target);
return ret; return ret;
} }

2
arch/arm64/kernel/signal.c
View File

@ -475,7 +475,7 @@ static int restore_za_context(struct user_ctxs *user)
fpsimd_flush_task_state(current); fpsimd_flush_task_state(current);
/* From now, fpsimd_thread_switch() won't touch thread.sve_state */ /* From now, fpsimd_thread_switch() won't touch thread.sve_state */
sme_alloc(current); sme_alloc(current, true);
if (!current->thread.sme_state) { if (!current->thread.sme_state) {
current->thread.svcr &= ~SVCR_ZA_MASK; current->thread.svcr &= ~SVCR_ZA_MASK;
clear_thread_flag(TIF_SME); clear_thread_flag(TIF_SME);

61
arch/arm64/kvm/arm.c
View File

@ -55,7 +55,7 @@ DECLARE_KVM_NVHE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
static bool vgic_present, kvm_arm_initialised; static bool vgic_present, kvm_arm_initialised;
static DEFINE_PER_CPU(unsigned char, kvm_arm_hardware_enabled); static DEFINE_PER_CPU(unsigned char, kvm_hyp_initialized);
DEFINE_STATIC_KEY_FALSE(userspace_irqchip_in_use); DEFINE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
bool is_kvm_arm_initialised(void) bool is_kvm_arm_initialised(void)
@ -1864,18 +1864,24 @@ static void cpu_hyp_reinit(void)
cpu_hyp_init_features(); cpu_hyp_init_features();
} }
static void _kvm_arch_hardware_enable(void *discard) static void cpu_hyp_init(void *discard)
{ {
if (!__this_cpu_read(kvm_arm_hardware_enabled)) { if (!__this_cpu_read(kvm_hyp_initialized)) {
cpu_hyp_reinit(); cpu_hyp_reinit();
__this_cpu_write(kvm_arm_hardware_enabled, 1); __this_cpu_write(kvm_hyp_initialized, 1);
}
}
static void cpu_hyp_uninit(void *discard)
{
if (__this_cpu_read(kvm_hyp_initialized)) {
cpu_hyp_reset();
__this_cpu_write(kvm_hyp_initialized, 0);
} }
} }
int kvm_arch_hardware_enable(void) int kvm_arch_hardware_enable(void)
{ {
int was_enabled;
/* /*
* Most calls to this function are made with migration * Most calls to this function are made with migration
* disabled, but not with preemption disabled. The former is * disabled, but not with preemption disabled. The former is
@ -1884,36 +1890,23 @@ int kvm_arch_hardware_enable(void)
*/ */
preempt_disable(); preempt_disable();
was_enabled = __this_cpu_read(kvm_arm_hardware_enabled); cpu_hyp_init(NULL);
_kvm_arch_hardware_enable(NULL);
if (!was_enabled) { kvm_vgic_cpu_up();
kvm_vgic_cpu_up(); kvm_timer_cpu_up();
kvm_timer_cpu_up();
}
preempt_enable(); preempt_enable();
return 0; return 0;
} }
static void _kvm_arch_hardware_disable(void *discard)
{
if (__this_cpu_read(kvm_arm_hardware_enabled)) {
cpu_hyp_reset();
__this_cpu_write(kvm_arm_hardware_enabled, 0);
}
}
void kvm_arch_hardware_disable(void) void kvm_arch_hardware_disable(void)
{ {
if (__this_cpu_read(kvm_arm_hardware_enabled)) { kvm_timer_cpu_down();
kvm_timer_cpu_down(); kvm_vgic_cpu_down();
kvm_vgic_cpu_down();
}
if (!is_protected_kvm_enabled()) if (!is_protected_kvm_enabled())
_kvm_arch_hardware_disable(NULL); cpu_hyp_uninit(NULL);
} }
#ifdef CONFIG_CPU_PM #ifdef CONFIG_CPU_PM
@ -1922,16 +1915,16 @@ static int hyp_init_cpu_pm_notifier(struct notifier_block *self,
void *v) void *v)
{ {
/* /*
* kvm_arm_hardware_enabled is left with its old value over * kvm_hyp_initialized is left with its old value over
* PM_ENTER->PM_EXIT. It is used to indicate PM_EXIT should * PM_ENTER->PM_EXIT. It is used to indicate PM_EXIT should
* re-enable hyp. * re-enable hyp.
*/ */
switch (cmd) { switch (cmd) {
case CPU_PM_ENTER: case CPU_PM_ENTER:
if (__this_cpu_read(kvm_arm_hardware_enabled)) if (__this_cpu_read(kvm_hyp_initialized))
/* /*
* don't update kvm_arm_hardware_enabled here * don't update kvm_hyp_initialized here
* so that the hardware will be re-enabled * so that the hyp will be re-enabled
* when we resume. See below. * when we resume. See below.
*/ */
cpu_hyp_reset(); cpu_hyp_reset();
@ -1939,8 +1932,8 @@ static int hyp_init_cpu_pm_notifier(struct notifier_block *self,
return NOTIFY_OK; return NOTIFY_OK;
case CPU_PM_ENTER_FAILED: case CPU_PM_ENTER_FAILED:
case CPU_PM_EXIT: case CPU_PM_EXIT:
if (__this_cpu_read(kvm_arm_hardware_enabled)) if (__this_cpu_read(kvm_hyp_initialized))
/* The hardware was enabled before suspend. */ /* The hyp was enabled before suspend. */
cpu_hyp_reinit(); cpu_hyp_reinit();
return NOTIFY_OK; return NOTIFY_OK;
@ -2021,7 +2014,7 @@ static int __init init_subsystems(void)
/* /*
* Enable hardware so that subsystem initialisation can access EL2. * Enable hardware so that subsystem initialisation can access EL2.
*/ */
on_each_cpu(_kvm_arch_hardware_enable, NULL, 1); on_each_cpu(cpu_hyp_init, NULL, 1);
/* /*
* Register CPU lower-power notifier * Register CPU lower-power notifier
@ -2059,7 +2052,7 @@ out:
hyp_cpu_pm_exit(); hyp_cpu_pm_exit();
if (err || !is_protected_kvm_enabled()) if (err || !is_protected_kvm_enabled())
on_each_cpu(_kvm_arch_hardware_disable, NULL, 1); on_each_cpu(cpu_hyp_uninit, NULL, 1);
return err; return err;
} }
@ -2097,7 +2090,7 @@ static int __init do_pkvm_init(u32 hyp_va_bits)
* The stub hypercalls are now disabled, so set our local flag to * The stub hypercalls are now disabled, so set our local flag to
* prevent a later re-init attempt in kvm_arch_hardware_enable(). * prevent a later re-init attempt in kvm_arch_hardware_enable().
*/ */
__this_cpu_write(kvm_arm_hardware_enabled, 1); __this_cpu_write(kvm_hyp_initialized, 1);
preempt_enable(); preempt_enable();
return ret; return ret;

1
arch/arm64/kvm/hyp/include/hyp/switch.h
View File

@ -457,6 +457,7 @@ static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
*/ */
val &= ~(TCR_HD | TCR_HA); val &= ~(TCR_HD | TCR_HA);
write_sysreg_el1(val, SYS_TCR); write_sysreg_el1(val, SYS_TCR);
__kvm_skip_instr(vcpu);
return true; return true;
} }

15
arch/arm64/kvm/hyp/nvhe/ffa.c
View File

@ -705,7 +705,20 @@ int hyp_ffa_init(void *pages)
if (res.a0 == FFA_RET_NOT_SUPPORTED) if (res.a0 == FFA_RET_NOT_SUPPORTED)
return 0; return 0;
if (res.a0 != FFA_VERSION_1_0) /*
* Firmware returns the maximum supported version of the FF-A
* implementation. Check that the returned version is
* backwards-compatible with the hyp according to the rules in DEN0077A
* v1.1 REL0 13.2.1.
*
* Of course, things are never simple when dealing with firmware. v1.1
* broke ABI with v1.0 on several structures, which is itself
* incompatible with the aforementioned versioning scheme. The
* expectation is that v1.x implementations that do not support the v1.0
* ABI return NOT_SUPPORTED rather than a version number, according to
* DEN0077A v1.1 REL0 18.6.4.
*/
if (FFA_MAJOR_VERSION(res.a0) != 1)
return -EOPNOTSUPP; return -EOPNOTSUPP;
arm_smccc_1_1_smc(FFA_ID_GET, 0, 0, 0, 0, 0, 0, 0, &res); arm_smccc_1_1_smc(FFA_ID_GET, 0, 0, 0, 0, 0, 0, 0, &res);

2
arch/arm64/kvm/hyp/nvhe/switch.c
View File

@ -63,7 +63,7 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
__activate_traps_fpsimd32(vcpu); __activate_traps_fpsimd32(vcpu);
} }
write_sysreg(val, cptr_el2); kvm_write_cptr_el2(val);
write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2);
if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {

3
arch/ia64/include/asm/processor.h
View File

@ -634,7 +634,6 @@ ia64_imva (void *addr)
#define ARCH_HAS_PREFETCH #define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW #define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH
#define PREFETCH_STRIDE L1_CACHE_BYTES #define PREFETCH_STRIDE L1_CACHE_BYTES
static inline void static inline void
@ -649,8 +648,6 @@ prefetchw (const void *x)
ia64_lfetch_excl(ia64_lfhint_none, x); ia64_lfetch_excl(ia64_lfhint_none, x);
} }
#define spin_lock_prefetch(x) prefetchw(x)
extern unsigned long boot_option_idle_override; extern unsigned long boot_option_idle_override;
enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT, enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,

2
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
View File

@ -58,8 +58,6 @@
#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) #define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
#define ARCH_HAS_SPINLOCK_PREFETCH 1
#define spin_lock_prefetch(x) prefetch(x)
#define PREFETCH_STRIDE 128 #define PREFETCH_STRIDE 128
#ifdef __OCTEON__ #ifdef __OCTEON__

2
arch/parisc/Kconfig.debug
View File

@ -2,7 +2,7 @@
# #
config LIGHTWEIGHT_SPINLOCK_CHECK config LIGHTWEIGHT_SPINLOCK_CHECK
bool "Enable lightweight spinlock checks" bool "Enable lightweight spinlock checks"
depends on SMP && !DEBUG_SPINLOCK depends on DEBUG_KERNEL && SMP && !DEBUG_SPINLOCK
default y default y
help help
Add checks with low performance impact to the spinlock functions Add checks with low performance impact to the spinlock functions

10
arch/parisc/boot/compressed/misc.c
View File

@ -117,7 +117,7 @@ char *strchr(const char *s, int c)
return NULL; return NULL;
} }
int puts(const char *s) static int puts(const char *s)
{ {
const char *nuline = s; const char *nuline = s;
@ -172,7 +172,7 @@ static int print_num(unsigned long num, int base)
return 0; return 0;
} }
int printf(const char *fmt, ...) static int printf(const char *fmt, ...)
{ {
va_list args; va_list args;
int i = 0; int i = 0;
@ -204,13 +204,13 @@ void abort(void)
} }
#undef malloc #undef malloc
void *malloc(size_t size) static void *malloc(size_t size)
{ {
return malloc_gzip(size); return malloc_gzip(size);
} }
#undef free #undef free
void free(void *ptr) static void free(void *ptr)
{ {
return free_gzip(ptr); return free_gzip(ptr);
} }
@ -278,7 +278,7 @@ static void parse_elf(void *output)
free(phdrs); free(phdrs);
} }
unsigned long decompress_kernel(unsigned int started_wide, asmlinkage unsigned long __visible decompress_kernel(unsigned int started_wide,
unsigned int command_line, unsigned int command_line,
const unsigned int rd_start, const unsigned int rd_start,
const unsigned int rd_end) const unsigned int rd_end)

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