From 63fb606a59a4e51572b2f34589b4afd00536f185 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 4 Oct 2022 12:53:28 -0500 Subject: [PATCH] arm: dts: socfpga: remove "clk-phase" in sdmmc_clk Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't need the clk-phase in the sdmmc_clk anymore. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 1 - arch/arm/boot/dts/socfpga_arria10.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 57a5d6c924b1..1d4a42cef483 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -453,7 +453,6 @@ compatible = "altr,socfpga-gate-clk"; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; clk-gate = <0xa0 8>; - clk-phase = <0 135>; }; sdmmc_clk_divided: sdmmc_clk_divided { diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index a06211fcb5c3..cc7d4a62dde7 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -365,7 +365,6 @@ compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; - clk-phase = <0 135>; }; qspi_clk: qspi_clk {