RISC-V: Add arch functions for non-retentive suspend entry/exit
The hart registers and CSRs are not preserved in non-retentative suspend state so we provide arch specific helper functions which will save/restore hart context upon entry/exit to non-retentive suspend state. These helper functions can be used by cpuidle drivers for non-retentive suspend entry/exit. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Anup Patel
Palmer Dabbelt
parent
e1de2c93e7
commit
63b13e64a8
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@ -67,4 +67,31 @@
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#error "Unexpected __SIZEOF_SHORT__"
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#endif
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#ifdef __ASSEMBLY__
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/* Common assembly source macros */
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#ifdef CONFIG_XIP_KERNEL
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.macro XIP_FIXUP_OFFSET reg
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REG_L t0, _xip_fixup
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add \reg, \reg, t0
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.endm
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.macro XIP_FIXUP_FLASH_OFFSET reg
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la t1, __data_loc
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li t0, XIP_OFFSET_MASK
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and t1, t1, t0
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li t1, XIP_OFFSET
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sub t0, t0, t1
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sub \reg, \reg, t0
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.endm
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_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
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#else
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.macro XIP_FIXUP_OFFSET reg
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.endm
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.macro XIP_FIXUP_FLASH_OFFSET reg
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.endm
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#endif /* CONFIG_XIP_KERNEL */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_ASM_H */
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@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*/
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#ifndef _ASM_RISCV_SUSPEND_H
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#define _ASM_RISCV_SUSPEND_H
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#include <asm/ptrace.h>
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struct suspend_context {
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/* Saved and restored by low-level functions */
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struct pt_regs regs;
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/* Saved and restored by high-level functions */
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unsigned long scratch;
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unsigned long tvec;
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unsigned long ie;
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#ifdef CONFIG_MMU
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unsigned long satp;
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#endif
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};
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/* Low-level CPU suspend entry function */
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int __cpu_suspend_enter(struct suspend_context *context);
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/* High-level CPU suspend which will save context and call finish() */
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int cpu_suspend(unsigned long arg,
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int (*finish)(unsigned long arg,
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unsigned long entry,
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unsigned long context));
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/* Low-level CPU resume entry function */
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int __cpu_resume_enter(unsigned long hartid, unsigned long context);
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#endif
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@ -48,6 +48,8 @@ obj-$(CONFIG_RISCV_BOOT_SPINWAIT) += cpu_ops_spinwait.o
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obj-$(CONFIG_MODULES) += module.o
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obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
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obj-$(CONFIG_CPU_PM) += suspend_entry.o suspend.o
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obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
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obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
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@ -13,6 +13,7 @@
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#include <asm/thread_info.h>
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#include <asm/ptrace.h>
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#include <asm/cpu_ops_sbi.h>
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#include <asm/suspend.h>
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void asm_offsets(void);
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@ -113,6 +114,8 @@ void asm_offsets(void)
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OFFSET(PT_BADADDR, pt_regs, badaddr);
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OFFSET(PT_CAUSE, pt_regs, cause);
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OFFSET(SUSPEND_CONTEXT_REGS, suspend_context, regs);
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OFFSET(KVM_ARCH_GUEST_ZERO, kvm_vcpu_arch, guest_context.zero);
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OFFSET(KVM_ARCH_GUEST_RA, kvm_vcpu_arch, guest_context.ra);
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OFFSET(KVM_ARCH_GUEST_SP, kvm_vcpu_arch, guest_context.sp);
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@ -16,27 +16,6 @@
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#include <asm/image.h>
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#include "efi-header.S"
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#ifdef CONFIG_XIP_KERNEL
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.macro XIP_FIXUP_OFFSET reg
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REG_L t0, _xip_fixup
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add \reg, \reg, t0
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.endm
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.macro XIP_FIXUP_FLASH_OFFSET reg
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la t1, __data_loc
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li t0, XIP_OFFSET_MASK
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and t1, t1, t0
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li t1, XIP_OFFSET
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sub t0, t0, t1
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sub \reg, \reg, t0
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.endm
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_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
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#else
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.macro XIP_FIXUP_OFFSET reg
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.endm
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.macro XIP_FIXUP_FLASH_OFFSET reg
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.endm
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#endif /* CONFIG_XIP_KERNEL */
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__HEAD
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ENTRY(_start)
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/*
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@ -0,0 +1,87 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*/
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#include <linux/ftrace.h>
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#include <asm/csr.h>
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#include <asm/suspend.h>
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static void suspend_save_csrs(struct suspend_context *context)
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{
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context->scratch = csr_read(CSR_SCRATCH);
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context->tvec = csr_read(CSR_TVEC);
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context->ie = csr_read(CSR_IE);
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/*
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* No need to save/restore IP CSR (i.e. MIP or SIP) because:
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*
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* 1. For no-MMU (M-mode) kernel, the bits in MIP are set by
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* external devices (such as interrupt controller, timer, etc).
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* 2. For MMU (S-mode) kernel, the bits in SIP are set by
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* M-mode firmware and external devices (such as interrupt
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* controller, etc).
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*/
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#ifdef CONFIG_MMU
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context->satp = csr_read(CSR_SATP);
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#endif
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}
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static void suspend_restore_csrs(struct suspend_context *context)
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{
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csr_write(CSR_SCRATCH, context->scratch);
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csr_write(CSR_TVEC, context->tvec);
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csr_write(CSR_IE, context->ie);
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#ifdef CONFIG_MMU
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csr_write(CSR_SATP, context->satp);
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#endif
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}
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int cpu_suspend(unsigned long arg,
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int (*finish)(unsigned long arg,
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unsigned long entry,
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unsigned long context))
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{
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int rc = 0;
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struct suspend_context context = { 0 };
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/* Finisher should be non-NULL */
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if (!finish)
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return -EINVAL;
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/* Save additional CSRs*/
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suspend_save_csrs(&context);
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/*
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* Function graph tracer state gets incosistent when the kernel
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* calls functions that never return (aka finishers) hence disable
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* graph tracing during their execution.
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*/
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pause_graph_tracing();
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/* Save context on stack */
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if (__cpu_suspend_enter(&context)) {
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/* Call the finisher */
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rc = finish(arg, __pa_symbol(__cpu_resume_enter),
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(ulong)&context);
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/*
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* Should never reach here, unless the suspend finisher
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* fails. Successful cpu_suspend() should return from
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* __cpu_resume_entry()
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*/
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if (!rc)
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rc = -EOPNOTSUPP;
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}
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/* Enable function graph tracer */
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unpause_graph_tracing();
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/* Restore additional CSRs */
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suspend_restore_csrs(&context);
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return rc;
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}
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@ -0,0 +1,124 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*/
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#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/csr.h>
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.text
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.altmacro
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.option norelax
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ENTRY(__cpu_suspend_enter)
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/* Save registers (except A0 and T0-T6) */
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REG_S ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
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REG_S sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
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REG_S gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
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REG_S tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
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REG_S s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
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REG_S s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
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REG_S a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
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REG_S a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
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REG_S a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
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REG_S a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
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REG_S a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
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REG_S a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
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REG_S a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
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REG_S s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
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REG_S s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
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REG_S s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
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REG_S s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
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REG_S s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
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REG_S s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
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REG_S s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
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REG_S s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
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REG_S s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
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REG_S s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
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/* Save CSRs */
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csrr t0, CSR_EPC
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REG_S t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
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csrr t0, CSR_STATUS
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REG_S t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
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csrr t0, CSR_TVAL
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REG_S t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
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csrr t0, CSR_CAUSE
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REG_S t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
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/* Return non-zero value */
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li a0, 1
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/* Return to C code */
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ret
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END(__cpu_suspend_enter)
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ENTRY(__cpu_resume_enter)
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/* Load the global pointer */
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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#ifdef CONFIG_MMU
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/* Save A0 and A1 */
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add t0, a0, zero
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add t1, a1, zero
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/* Enable MMU */
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la a0, swapper_pg_dir
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XIP_FIXUP_OFFSET a0
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call relocate_enable_mmu
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/* Restore A0 and A1 */
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add a0, t0, zero
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add a1, t1, zero
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#endif
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/* Make A0 point to suspend context */
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add a0, a1, zero
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/* Restore CSRs */
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REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
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csrw CSR_EPC, t0
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REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
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csrw CSR_STATUS, t0
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REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
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csrw CSR_TVAL, t0
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REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
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csrw CSR_CAUSE, t0
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/* Restore registers (except A0 and T0-T6) */
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REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
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REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
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REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
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REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
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REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
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REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
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REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
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REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
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REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
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REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
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REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
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REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
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REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
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REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
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REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
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REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
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REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
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REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
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REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
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REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
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REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
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REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
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REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
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/* Return zero value */
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add a0, zero, zero
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/* Return to C code */
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ret
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END(__cpu_resume_enter)
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