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MIPS: CPS: Copy EVA configuration when starting secondary VPs. 

When starting secondary VPEs which support EVA and the SegCtl registers,
copy the memory segmentation configuration from the running VPE to ensure
that all VPEs in the core have a consistent virtual memory map.

The EVA configuration of secondary cores is dealt with when starting the
core via the CM.

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13291/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Matt Redfearn 2016-05-18 17:12:36 +01:00 committed by Ralf Baechle
parent 5c33f8b2e5
commit 63a8802f4f
1 changed files with 15 additions and 0 deletions
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15
arch/mips/kernel/cps-vec.S
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@ -441,6 +441,21 @@ LEAF(mips_cps_boot_vpes)
mfc0 t0, CP0_CONFIG mfc0 t0, CP0_CONFIG
mttc0 t0, CP0_CONFIG mttc0 t0, CP0_CONFIG
/*
* Copy the EVA config from this VPE if the CPU supports it.
* CONFIG3 must exist to be running MT startup - just read it.
*/
mfc0 t0, CP0_CONFIG, 3
and t0, t0, MIPS_CONF3_SC
beqz t0, 3f
nop
mfc0 t0, CP0_SEGCTL0
mttc0 t0, CP0_SEGCTL0
mfc0 t0, CP0_SEGCTL1
mttc0 t0, CP0_SEGCTL1
mfc0 t0, CP0_SEGCTL2
mttc0 t0, CP0_SEGCTL2
3:
/* Ensure no software interrupts are pending */ /* Ensure no software interrupts are pending */
mttc0 zero, CP0_CAUSE mttc0 zero, CP0_CAUSE
mttc0 zero, CP0_STATUS mttc0 zero, CP0_STATUS