Merge branch 'wireless-next-2.6' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-2.6
This commit is contained in:
commit
6392cb387c
|
@ -13,6 +13,7 @@ iwlagn-objs += iwl-5000.o
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iwlagn-objs += iwl-6000.o
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iwlagn-objs += iwl-1000.o
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iwlagn-objs += iwl-2000.o
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iwlagn-objs += iwl-pci.o
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iwlagn-$(CONFIG_IWLWIFI_DEBUGFS) += iwl-debugfs.o
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iwlagn-$(CONFIG_IWLWIFI_DEVICE_TRACING) += iwl-devtrace.o
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|
|
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@ -27,8 +27,6 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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@ -194,8 +192,6 @@ static struct iwl_lib_ops iwl1000_lib = {
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.temp_ops = {
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.temperature = iwlagn_temperature,
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},
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.txfifo_flush = iwlagn_txfifo_flush,
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.dev_txfifo_flush = iwlagn_dev_txfifo_flush,
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};
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static const struct iwl_ops iwl1000_ops = {
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@ -27,8 +27,6 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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@ -76,21 +74,7 @@ static void iwl2000_set_ct_threshold(struct iwl_priv *priv)
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/* NIC configuration for 2000 series */
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static void iwl2000_nic_config(struct iwl_priv *priv)
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{
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u16 radio_cfg;
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radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
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/* write radio config values to register */
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if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX)
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
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EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
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EEPROM_RF_CFG_DASH_MSK(radio_cfg));
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/* set CSR_HW_CONFIG_REG for uCode use */
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
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CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
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iwl_rf_config(priv);
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if (priv->cfg->iq_invert)
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iwl_set_bit(priv, CSR_GP_DRIVER_REG,
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@ -204,8 +188,6 @@ static struct iwl_lib_ops iwl2000_lib = {
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.temp_ops = {
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.temperature = iwlagn_temperature,
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},
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.txfifo_flush = iwlagn_txfifo_flush,
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.dev_txfifo_flush = iwlagn_dev_txfifo_flush,
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};
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static const struct iwl_ops iwl2000_ops = {
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|
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@ -27,8 +27,6 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/skbuff.h>
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@ -66,24 +64,11 @@
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static void iwl5000_nic_config(struct iwl_priv *priv)
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{
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unsigned long flags;
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u16 radio_cfg;
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iwl_rf_config(priv);
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spin_lock_irqsave(&priv->lock, flags);
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radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
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/* write radio config values to register */
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if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
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EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
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EEPROM_RF_CFG_DASH_MSK(radio_cfg));
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/* set CSR_HW_CONFIG_REG for uCode use */
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
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CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
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/* W/A : NIC is stuck in a reset state after Early PCIe power off
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* (PCIe power is lost before PERST# is asserted),
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* causing ME FW to lose ownership and not being able to obtain it back.
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|
@ -361,8 +346,6 @@ static struct iwl_lib_ops iwl5000_lib = {
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.temp_ops = {
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.temperature = iwlagn_temperature,
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},
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.txfifo_flush = iwlagn_txfifo_flush,
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.dev_txfifo_flush = iwlagn_dev_txfifo_flush,
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};
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static struct iwl_lib_ops iwl5150_lib = {
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@ -391,8 +374,6 @@ static struct iwl_lib_ops iwl5150_lib = {
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.temp_ops = {
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.temperature = iwl5150_temperature,
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},
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.txfifo_flush = iwlagn_txfifo_flush,
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.dev_txfifo_flush = iwlagn_dev_txfifo_flush,
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};
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static const struct iwl_ops iwl5000_ops = {
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|
|
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@ -27,8 +27,6 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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@ -97,21 +95,7 @@ static void iwl6150_additional_nic_config(struct iwl_priv *priv)
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/* NIC configuration for 6000 series */
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static void iwl6000_nic_config(struct iwl_priv *priv)
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{
|
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u16 radio_cfg;
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||||
|
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radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
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/* write radio config values to register */
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if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX)
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
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EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
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EEPROM_RF_CFG_DASH_MSK(radio_cfg));
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/* set CSR_HW_CONFIG_REG for uCode use */
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
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||||
CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
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iwl_rf_config(priv);
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/* no locking required for register write */
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if (priv->cfg->pa_type == IWL_PA_INTERNAL) {
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|
@ -301,8 +285,6 @@ static struct iwl_lib_ops iwl6000_lib = {
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.temp_ops = {
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.temperature = iwlagn_temperature,
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},
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.txfifo_flush = iwlagn_txfifo_flush,
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.dev_txfifo_flush = iwlagn_dev_txfifo_flush,
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};
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static struct iwl_lib_ops iwl6030_lib = {
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@ -333,8 +315,6 @@ static struct iwl_lib_ops iwl6030_lib = {
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|||
.temp_ops = {
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.temperature = iwlagn_temperature,
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},
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.txfifo_flush = iwlagn_txfifo_flush,
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.dev_txfifo_flush = iwlagn_dev_txfifo_flush,
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};
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static struct iwl_nic_ops iwl6050_nic_ops = {
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||||
|
|
|
@ -81,13 +81,6 @@
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|||
/* RSSI to dBm */
|
||||
#define IWLAGN_RSSI_OFFSET 44
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|
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/* PCI registers */
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#define PCI_CFG_RETRY_TIMEOUT 0x041
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/* PCI register values */
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#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
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#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
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#define IWLAGN_DEFAULT_TX_RETRY 15
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/* Limit range of txpower output target to be between these values */
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|
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@ -44,7 +44,7 @@
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void iwl_free_isr_ict(struct iwl_priv *priv)
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{
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if (priv->_agn.ict_tbl_vir) {
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dma_free_coherent(&priv->pci_dev->dev,
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dma_free_coherent(priv->bus.dev,
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(sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
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priv->_agn.ict_tbl_vir,
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priv->_agn.ict_tbl_dma);
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@ -61,7 +61,7 @@ int iwl_alloc_isr_ict(struct iwl_priv *priv)
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|||
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/* allocate shrared data table */
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priv->_agn.ict_tbl_vir =
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dma_alloc_coherent(&priv->pci_dev->dev,
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dma_alloc_coherent(priv->bus.dev,
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(sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
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&priv->_agn.ict_tbl_dma, GFP_KERNEL);
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if (!priv->_agn.ict_tbl_vir)
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|
|
|
@ -624,6 +624,7 @@ struct iwl_mod_params iwlagn_mod_params = {
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.plcp_check = true,
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.bt_coex_active = true,
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.no_sleep_autoadjust = true,
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.power_level = IWL_POWER_INDEX_1,
|
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/* the rest are 0 by default */
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};
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|
@ -639,9 +640,9 @@ void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
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/* In the reset function, these buffers may have been allocated
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* to an SKB, so we need to unmap and free potential storage */
|
||||
if (rxq->pool[i].page != NULL) {
|
||||
pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
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dma_unmap_page(priv->bus.dev, rxq->pool[i].page_dma,
|
||||
PAGE_SIZE << priv->hw_params.rx_page_order,
|
||||
PCI_DMA_FROMDEVICE);
|
||||
DMA_FROM_DEVICE);
|
||||
__iwl_free_pages(priv, rxq->pool[i].page);
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rxq->pool[i].page = NULL;
|
||||
}
|
||||
|
@ -913,9 +914,9 @@ void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
|
|||
BUG_ON(rxb->page);
|
||||
rxb->page = page;
|
||||
/* Get physical address of the RB */
|
||||
rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
|
||||
rxb->page_dma = dma_map_page(priv->bus.dev, page, 0,
|
||||
PAGE_SIZE << priv->hw_params.rx_page_order,
|
||||
PCI_DMA_FROMDEVICE);
|
||||
DMA_FROM_DEVICE);
|
||||
/* dma address must be no more than 36 bits */
|
||||
BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
|
||||
/* and also 256 byte aligned! */
|
||||
|
@ -958,17 +959,18 @@ void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
|
|||
int i;
|
||||
for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
|
||||
if (rxq->pool[i].page != NULL) {
|
||||
pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
|
||||
dma_unmap_page(priv->bus.dev, rxq->pool[i].page_dma,
|
||||
PAGE_SIZE << priv->hw_params.rx_page_order,
|
||||
PCI_DMA_FROMDEVICE);
|
||||
DMA_FROM_DEVICE);
|
||||
__iwl_free_pages(priv, rxq->pool[i].page);
|
||||
rxq->pool[i].page = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
|
||||
rxq->bd_dma);
|
||||
dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
|
||||
dma_free_coherent(priv->bus.dev, 4 * RX_QUEUE_SIZE,
|
||||
rxq->bd, rxq->bd_dma);
|
||||
dma_free_coherent(priv->bus.dev,
|
||||
sizeof(struct iwl_rb_status),
|
||||
rxq->rb_stts, rxq->rb_stts_dma);
|
||||
rxq->bd = NULL;
|
||||
rxq->rb_stts = NULL;
|
||||
|
@ -1530,8 +1532,17 @@ int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
|
|||
might_sleep();
|
||||
|
||||
memset(&flush_cmd, 0, sizeof(flush_cmd));
|
||||
flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
|
||||
IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
|
||||
if (flush_control & BIT(IWL_RXON_CTX_BSS))
|
||||
flush_cmd.fifo_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK |
|
||||
IWL_SCD_BE_MSK | IWL_SCD_BK_MSK |
|
||||
IWL_SCD_MGMT_MSK;
|
||||
if ((flush_control & BIT(IWL_RXON_CTX_PAN)) &&
|
||||
(priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)))
|
||||
flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK |
|
||||
IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK |
|
||||
IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK |
|
||||
IWL_PAN_SCD_MULTICAST_MSK;
|
||||
|
||||
if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
|
||||
flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
|
||||
|
||||
|
@ -1546,7 +1557,7 @@ void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
|
|||
{
|
||||
mutex_lock(&priv->mutex);
|
||||
ieee80211_stop_queues(priv->hw);
|
||||
if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
|
||||
if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) {
|
||||
IWL_ERR(priv, "flush request fail\n");
|
||||
goto done;
|
||||
}
|
||||
|
|
|
@ -716,10 +716,10 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
|
|||
|
||||
/* Physical address of this Tx command's header (not MAC header!),
|
||||
* within command buffer array. */
|
||||
txcmd_phys = pci_map_single(priv->pci_dev,
|
||||
txcmd_phys = dma_map_single(priv->bus.dev,
|
||||
&out_cmd->hdr, firstlen,
|
||||
PCI_DMA_BIDIRECTIONAL);
|
||||
if (unlikely(pci_dma_mapping_error(priv->pci_dev, txcmd_phys)))
|
||||
DMA_BIDIRECTIONAL);
|
||||
if (unlikely(dma_mapping_error(priv->bus.dev, txcmd_phys)))
|
||||
goto drop_unlock_sta;
|
||||
dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
|
||||
dma_unmap_len_set(out_meta, len, firstlen);
|
||||
|
@ -735,13 +735,13 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
|
|||
* if any (802.11 null frames have no payload). */
|
||||
secondlen = skb->len - hdr_len;
|
||||
if (secondlen > 0) {
|
||||
phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
|
||||
secondlen, PCI_DMA_TODEVICE);
|
||||
if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) {
|
||||
pci_unmap_single(priv->pci_dev,
|
||||
phys_addr = dma_map_single(priv->bus.dev, skb->data + hdr_len,
|
||||
secondlen, DMA_TO_DEVICE);
|
||||
if (unlikely(dma_mapping_error(priv->bus.dev, phys_addr))) {
|
||||
dma_unmap_single(priv->bus.dev,
|
||||
dma_unmap_addr(out_meta, mapping),
|
||||
dma_unmap_len(out_meta, len),
|
||||
PCI_DMA_BIDIRECTIONAL);
|
||||
DMA_BIDIRECTIONAL);
|
||||
goto drop_unlock_sta;
|
||||
}
|
||||
}
|
||||
|
@ -764,8 +764,8 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
|
|||
offsetof(struct iwl_tx_cmd, scratch);
|
||||
|
||||
/* take back ownership of DMA buffer to enable update */
|
||||
pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
|
||||
firstlen, PCI_DMA_BIDIRECTIONAL);
|
||||
dma_sync_single_for_cpu(priv->bus.dev, txcmd_phys, firstlen,
|
||||
DMA_BIDIRECTIONAL);
|
||||
tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
|
||||
tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
|
||||
|
||||
|
@ -780,8 +780,8 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
|
|||
iwlagn_txq_update_byte_cnt_tbl(priv, txq,
|
||||
le16_to_cpu(tx_cmd->len));
|
||||
|
||||
pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
|
||||
firstlen, PCI_DMA_BIDIRECTIONAL);
|
||||
dma_sync_single_for_device(priv->bus.dev, txcmd_phys, firstlen,
|
||||
DMA_BIDIRECTIONAL);
|
||||
|
||||
trace_iwlwifi_dev_tx(priv,
|
||||
&((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
|
||||
|
@ -834,8 +834,8 @@ drop_unlock_priv:
|
|||
static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
|
||||
struct iwl_dma_ptr *ptr, size_t size)
|
||||
{
|
||||
ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
|
||||
GFP_KERNEL);
|
||||
ptr->addr = dma_alloc_coherent(priv->bus.dev, size,
|
||||
&ptr->dma, GFP_KERNEL);
|
||||
if (!ptr->addr)
|
||||
return -ENOMEM;
|
||||
ptr->size = size;
|
||||
|
@ -848,7 +848,7 @@ static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
|
|||
if (unlikely(!ptr->addr))
|
||||
return;
|
||||
|
||||
dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
|
||||
dma_free_coherent(priv->bus.dev, ptr->size, ptr->addr, ptr->dma);
|
||||
memset(ptr, 0, sizeof(*ptr));
|
||||
}
|
||||
|
||||
|
|
|
@ -32,8 +32,6 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pci-aspm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/delay.h>
|
||||
|
@ -49,8 +47,6 @@
|
|||
|
||||
#include <asm/div64.h>
|
||||
|
||||
#define DRV_NAME "iwlagn"
|
||||
|
||||
#include "iwl-eeprom.h"
|
||||
#include "iwl-dev.h"
|
||||
#include "iwl-core.h"
|
||||
|
@ -59,6 +55,7 @@
|
|||
#include "iwl-sta.h"
|
||||
#include "iwl-agn-calib.h"
|
||||
#include "iwl-agn.h"
|
||||
#include "iwl-pci.h"
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
|
@ -440,10 +437,8 @@ static void iwl_bg_tx_flush(struct work_struct *work)
|
|||
if (!iwl_is_ready_rf(priv))
|
||||
return;
|
||||
|
||||
if (priv->cfg->ops->lib->txfifo_flush) {
|
||||
IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
|
||||
iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
|
||||
}
|
||||
IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
|
||||
iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -497,9 +492,9 @@ static void iwl_rx_handle(struct iwl_priv *priv)
|
|||
|
||||
rxq->queue[i] = NULL;
|
||||
|
||||
pci_unmap_page(priv->pci_dev, rxb->page_dma,
|
||||
dma_unmap_page(priv->bus.dev, rxb->page_dma,
|
||||
PAGE_SIZE << priv->hw_params.rx_page_order,
|
||||
PCI_DMA_FROMDEVICE);
|
||||
DMA_FROM_DEVICE);
|
||||
pkt = rxb_addr(rxb);
|
||||
|
||||
len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
|
||||
|
@ -581,9 +576,9 @@ static void iwl_rx_handle(struct iwl_priv *priv)
|
|||
* rx_free list for reuse later. */
|
||||
spin_lock_irqsave(&rxq->lock, flags);
|
||||
if (rxb->page != NULL) {
|
||||
rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
|
||||
rxb->page_dma = dma_map_page(priv->bus.dev, rxb->page,
|
||||
0, PAGE_SIZE << priv->hw_params.rx_page_order,
|
||||
PCI_DMA_FROMDEVICE);
|
||||
DMA_FROM_DEVICE);
|
||||
list_add_tail(&rxb->list, &rxq->rx_free);
|
||||
rxq->free_count++;
|
||||
} else
|
||||
|
@ -939,22 +934,28 @@ static struct attribute_group iwl_attribute_group = {
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
static void iwl_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
|
||||
static void iwl_free_fw_desc(struct iwl_priv *priv, struct fw_desc *desc)
|
||||
{
|
||||
if (desc->v_addr)
|
||||
dma_free_coherent(&pci_dev->dev, desc->len,
|
||||
dma_free_coherent(priv->bus.dev, desc->len,
|
||||
desc->v_addr, desc->p_addr);
|
||||
desc->v_addr = NULL;
|
||||
desc->len = 0;
|
||||
}
|
||||
|
||||
static void iwl_free_fw_img(struct pci_dev *pci_dev, struct fw_img *img)
|
||||
static void iwl_free_fw_img(struct iwl_priv *priv, struct fw_img *img)
|
||||
{
|
||||
iwl_free_fw_desc(pci_dev, &img->code);
|
||||
iwl_free_fw_desc(pci_dev, &img->data);
|
||||
iwl_free_fw_desc(priv, &img->code);
|
||||
iwl_free_fw_desc(priv, &img->data);
|
||||
}
|
||||
|
||||
static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc,
|
||||
static void iwl_dealloc_ucode(struct iwl_priv *priv)
|
||||
{
|
||||
iwl_free_fw_img(priv, &priv->ucode_rt);
|
||||
iwl_free_fw_img(priv, &priv->ucode_init);
|
||||
}
|
||||
|
||||
static int iwl_alloc_fw_desc(struct iwl_priv *priv, struct fw_desc *desc,
|
||||
const void *data, size_t len)
|
||||
{
|
||||
if (!len) {
|
||||
|
@ -962,21 +963,16 @@ static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
desc->v_addr = dma_alloc_coherent(&pci_dev->dev, len,
|
||||
desc->v_addr = dma_alloc_coherent(priv->bus.dev, len,
|
||||
&desc->p_addr, GFP_KERNEL);
|
||||
if (!desc->v_addr)
|
||||
return -ENOMEM;
|
||||
|
||||
desc->len = len;
|
||||
memcpy(desc->v_addr, data, len);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
|
||||
{
|
||||
iwl_free_fw_img(priv->pci_dev, &priv->ucode_rt);
|
||||
iwl_free_fw_img(priv->pci_dev, &priv->ucode_init);
|
||||
}
|
||||
|
||||
struct iwlagn_ucode_capabilities {
|
||||
u32 max_probe_length;
|
||||
u32 standard_phy_calibration_size;
|
||||
|
@ -1021,8 +1017,8 @@ static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
|
|||
priv->firmware_name);
|
||||
|
||||
return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
|
||||
&priv->pci_dev->dev, GFP_KERNEL, priv,
|
||||
iwl_ucode_callback);
|
||||
priv->bus.dev,
|
||||
GFP_KERNEL, priv, iwl_ucode_callback);
|
||||
}
|
||||
|
||||
struct iwlagn_firmware_pieces {
|
||||
|
@ -1443,19 +1439,19 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
|
|||
/* Runtime instructions and 2 copies of data:
|
||||
* 1) unmodified from disk
|
||||
* 2) backup cache for save/restore during power-downs */
|
||||
if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.code,
|
||||
if (iwl_alloc_fw_desc(priv, &priv->ucode_rt.code,
|
||||
pieces.inst, pieces.inst_size))
|
||||
goto err_pci_alloc;
|
||||
if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.data,
|
||||
if (iwl_alloc_fw_desc(priv, &priv->ucode_rt.data,
|
||||
pieces.data, pieces.data_size))
|
||||
goto err_pci_alloc;
|
||||
|
||||
/* Initialization instructions and data */
|
||||
if (pieces.init_size && pieces.init_data_size) {
|
||||
if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.code,
|
||||
if (iwl_alloc_fw_desc(priv, &priv->ucode_init.code,
|
||||
pieces.init, pieces.init_size))
|
||||
goto err_pci_alloc;
|
||||
if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.data,
|
||||
if (iwl_alloc_fw_desc(priv, &priv->ucode_init.data,
|
||||
pieces.init_data, pieces.init_data_size))
|
||||
goto err_pci_alloc;
|
||||
}
|
||||
|
@ -1524,7 +1520,7 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
|
|||
if (err)
|
||||
IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
|
||||
|
||||
err = sysfs_create_group(&priv->pci_dev->dev.kobj,
|
||||
err = sysfs_create_group(&(priv->bus.dev->kobj),
|
||||
&iwl_attribute_group);
|
||||
if (err) {
|
||||
IWL_ERR(priv, "failed to create sysfs device attributes\n");
|
||||
|
@ -1545,10 +1541,10 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
|
|||
|
||||
err_pci_alloc:
|
||||
IWL_ERR(priv, "failed to allocate pci memory\n");
|
||||
iwl_dealloc_ucode_pci(priv);
|
||||
iwl_dealloc_ucode(priv);
|
||||
out_unbind:
|
||||
complete(&priv->_agn.firmware_loading_complete);
|
||||
device_release_driver(&priv->pci_dev->dev);
|
||||
device_release_driver(priv->bus.dev);
|
||||
release_firmware(ucode_raw);
|
||||
}
|
||||
|
||||
|
@ -2549,11 +2545,10 @@ static int iwl_mac_setup_register(struct iwl_priv *priv,
|
|||
WIPHY_FLAG_DISABLE_BEACON_HINTS |
|
||||
WIPHY_FLAG_IBSS_RSN;
|
||||
|
||||
/*
|
||||
* For now, disable PS by default because it affects
|
||||
* RX performance significantly.
|
||||
*/
|
||||
hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
|
||||
if (iwlagn_mod_params.power_save)
|
||||
hw->wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
|
||||
else
|
||||
hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
|
||||
|
||||
hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
|
||||
/* we create the 802.11 header and a zero-length SSID element */
|
||||
|
@ -3052,10 +3047,6 @@ static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
|
|||
mutex_lock(&priv->mutex);
|
||||
IWL_DEBUG_MAC80211(priv, "enter\n");
|
||||
|
||||
/* do not support "flush" */
|
||||
if (!priv->cfg->ops->lib->txfifo_flush)
|
||||
goto done;
|
||||
|
||||
if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
|
||||
IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
|
||||
goto done;
|
||||
|
@ -3071,7 +3062,7 @@ static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
|
|||
*/
|
||||
if (drop) {
|
||||
IWL_DEBUG_MAC80211(priv, "send flush command\n");
|
||||
if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
|
||||
if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) {
|
||||
IWL_ERR(priv, "flush request fail\n");
|
||||
goto done;
|
||||
}
|
||||
|
@ -3357,10 +3348,6 @@ struct ieee80211_ops iwlagn_hw_ops = {
|
|||
|
||||
static u32 iwl_hw_detect(struct iwl_priv *priv)
|
||||
{
|
||||
u8 rev_id;
|
||||
|
||||
pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
|
||||
IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
|
||||
return iwl_read32(priv, CSR_HW_REV);
|
||||
}
|
||||
|
||||
|
@ -3485,32 +3472,39 @@ static void iwl_init_context(struct iwl_priv *priv)
|
|||
BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
|
||||
}
|
||||
|
||||
static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
|
||||
struct iwl_cfg *cfg)
|
||||
{
|
||||
int err = 0;
|
||||
struct iwl_priv *priv;
|
||||
struct ieee80211_hw *hw;
|
||||
struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
|
||||
unsigned long flags;
|
||||
u16 pci_cmd, num_mac;
|
||||
u16 num_mac;
|
||||
u32 hw_rev;
|
||||
|
||||
/************************
|
||||
* 1. Allocating HW data
|
||||
************************/
|
||||
|
||||
hw = iwl_alloc_all(cfg);
|
||||
if (!hw) {
|
||||
err = -ENOMEM;
|
||||
goto out; }
|
||||
goto out;
|
||||
}
|
||||
|
||||
priv = hw->priv;
|
||||
|
||||
priv->bus.priv = priv;
|
||||
priv->bus.bus_specific = bus_specific;
|
||||
priv->bus.ops = bus_ops;
|
||||
priv->bus.irq = priv->bus.ops->get_irq(&priv->bus);
|
||||
priv->bus.ops->set_drv_data(&priv->bus, priv);
|
||||
priv->bus.dev = priv->bus.ops->get_dev(&priv->bus);
|
||||
|
||||
/* At this point both hw and priv are allocated. */
|
||||
|
||||
SET_IEEE80211_DEV(hw, &pdev->dev);
|
||||
SET_IEEE80211_DEV(hw, priv->bus.dev);
|
||||
|
||||
IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
|
||||
priv->cfg = cfg;
|
||||
priv->pci_dev = pdev;
|
||||
priv->inta_mask = CSR_INI_SET_MASK;
|
||||
|
||||
/* is antenna coupling more than 35dB ? */
|
||||
|
@ -3526,52 +3520,6 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
if (iwl_alloc_traffic_mem(priv))
|
||||
IWL_ERR(priv, "Not enough memory to generate traffic log\n");
|
||||
|
||||
/**************************
|
||||
* 2. Initializing PCI bus
|
||||
**************************/
|
||||
pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
|
||||
PCIE_LINK_STATE_CLKPM);
|
||||
|
||||
if (pci_enable_device(pdev)) {
|
||||
err = -ENODEV;
|
||||
goto out_ieee80211_free_hw;
|
||||
}
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
|
||||
if (!err)
|
||||
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
|
||||
if (err) {
|
||||
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (!err)
|
||||
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
/* both attempts failed: */
|
||||
if (err) {
|
||||
IWL_WARN(priv, "No suitable DMA available.\n");
|
||||
goto out_pci_disable_device;
|
||||
}
|
||||
}
|
||||
|
||||
err = pci_request_regions(pdev, DRV_NAME);
|
||||
if (err)
|
||||
goto out_pci_disable_device;
|
||||
|
||||
pci_set_drvdata(pdev, priv);
|
||||
|
||||
|
||||
/***********************
|
||||
* 3. Read REV register
|
||||
***********************/
|
||||
priv->hw_base = pci_iomap(pdev, 0, 0);
|
||||
if (!priv->hw_base) {
|
||||
err = -ENODEV;
|
||||
goto out_pci_release_regions;
|
||||
}
|
||||
|
||||
IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
|
||||
(unsigned long long) pci_resource_len(pdev, 0));
|
||||
IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
|
||||
|
||||
/* these spin locks will be used in apm_ops.init and EEPROM access
|
||||
* we should init now
|
||||
|
@ -3586,17 +3534,17 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
*/
|
||||
iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
|
||||
|
||||
/***********************
|
||||
* 3. Read REV register
|
||||
***********************/
|
||||
hw_rev = iwl_hw_detect(priv);
|
||||
IWL_INFO(priv, "Detected %s, REV=0x%X\n",
|
||||
priv->cfg->name, hw_rev);
|
||||
|
||||
/* We disable the RETRY_TIMEOUT register (0x41) to keep
|
||||
* PCI Tx retries from interfering with C3 CPU state */
|
||||
pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
|
||||
|
||||
if (iwl_prepare_card_hw(priv)) {
|
||||
err = -EIO;
|
||||
IWL_WARN(priv, "Failed, HW not ready\n");
|
||||
goto out_iounmap;
|
||||
goto out_free_traffic_mem;
|
||||
}
|
||||
|
||||
/*****************
|
||||
|
@ -3606,7 +3554,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
err = iwl_eeprom_init(priv, hw_rev);
|
||||
if (err) {
|
||||
IWL_ERR(priv, "Unable to init EEPROM\n");
|
||||
goto out_iounmap;
|
||||
goto out_free_traffic_mem;
|
||||
}
|
||||
err = iwl_eeprom_check_version(priv);
|
||||
if (err)
|
||||
|
@ -3636,6 +3584,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
* 5. Setup HW constants
|
||||
************************/
|
||||
if (iwl_set_hw_params(priv)) {
|
||||
err = -ENOENT;
|
||||
IWL_ERR(priv, "failed to set hw parameters\n");
|
||||
goto out_free_eeprom;
|
||||
}
|
||||
|
@ -3652,19 +3601,13 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
/********************
|
||||
* 7. Setup services
|
||||
********************/
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
iwl_disable_interrupts(priv);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
pci_enable_msi(priv->pci_dev);
|
||||
|
||||
iwl_alloc_isr_ict(priv);
|
||||
|
||||
err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
|
||||
IRQF_SHARED, DRV_NAME, priv);
|
||||
err = request_irq(priv->bus.irq, iwl_isr_ict, IRQF_SHARED,
|
||||
DRV_NAME, priv);
|
||||
if (err) {
|
||||
IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
|
||||
goto out_disable_msi;
|
||||
IWL_ERR(priv, "Error allocating IRQ %d\n", priv->bus.irq);
|
||||
goto out_uninit_drv;
|
||||
}
|
||||
|
||||
iwl_setup_deferred_work(priv);
|
||||
|
@ -3672,16 +3615,9 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
iwl_testmode_init(priv);
|
||||
|
||||
/*********************************************
|
||||
* 8. Enable interrupts and read RFKILL state
|
||||
* 8. Enable interrupts
|
||||
*********************************************/
|
||||
|
||||
/* enable rfkill interrupt: hw bug w/a */
|
||||
pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
|
||||
if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
|
||||
pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
|
||||
pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
|
||||
}
|
||||
|
||||
iwl_enable_rfkill_int(priv);
|
||||
|
||||
/* If platform's RF_KILL switch is NOT set to KILL */
|
||||
|
@ -3707,41 +3643,30 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
out_destroy_workqueue:
|
||||
destroy_workqueue(priv->workqueue);
|
||||
priv->workqueue = NULL;
|
||||
free_irq(priv->pci_dev->irq, priv);
|
||||
out_disable_msi:
|
||||
free_irq(priv->bus.irq, priv);
|
||||
iwl_free_isr_ict(priv);
|
||||
pci_disable_msi(priv->pci_dev);
|
||||
out_uninit_drv:
|
||||
iwl_uninit_drv(priv);
|
||||
out_free_eeprom:
|
||||
iwl_eeprom_free(priv);
|
||||
out_iounmap:
|
||||
pci_iounmap(pdev, priv->hw_base);
|
||||
out_pci_release_regions:
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
pci_release_regions(pdev);
|
||||
out_pci_disable_device:
|
||||
pci_disable_device(pdev);
|
||||
out_ieee80211_free_hw:
|
||||
out_free_traffic_mem:
|
||||
iwl_free_traffic_mem(priv);
|
||||
ieee80211_free_hw(priv->hw);
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
|
||||
static void __devexit iwl_pci_remove(struct pci_dev *pdev)
|
||||
void __devexit iwl_remove(struct iwl_priv * priv)
|
||||
{
|
||||
struct iwl_priv *priv = pci_get_drvdata(pdev);
|
||||
unsigned long flags;
|
||||
|
||||
if (!priv)
|
||||
return;
|
||||
|
||||
wait_for_completion(&priv->_agn.firmware_loading_complete);
|
||||
|
||||
IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
|
||||
|
||||
iwl_dbgfs_unregister(priv);
|
||||
sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
|
||||
sysfs_remove_group(&priv->bus.dev->kobj,
|
||||
&iwl_attribute_group);
|
||||
|
||||
/* ieee80211_unregister_hw call wil cause iwl_mac_stop to
|
||||
* to be called and iwl_down since we are removing the device
|
||||
|
@ -3771,7 +3696,7 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev)
|
|||
|
||||
iwl_synchronize_irq(priv);
|
||||
|
||||
iwl_dealloc_ucode_pci(priv);
|
||||
iwl_dealloc_ucode(priv);
|
||||
|
||||
if (priv->rxq.bd)
|
||||
iwlagn_rx_queue_free(priv, &priv->rxq);
|
||||
|
@ -3790,12 +3715,8 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev)
|
|||
priv->workqueue = NULL;
|
||||
iwl_free_traffic_mem(priv);
|
||||
|
||||
free_irq(priv->pci_dev->irq, priv);
|
||||
pci_disable_msi(priv->pci_dev);
|
||||
pci_iounmap(pdev, priv->hw_base);
|
||||
pci_release_regions(pdev);
|
||||
pci_disable_device(pdev);
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
free_irq(priv->bus.irq, priv);
|
||||
priv->bus.ops->set_drv_data(&priv->bus, NULL);
|
||||
|
||||
iwl_uninit_drv(priv);
|
||||
|
||||
|
@ -3812,206 +3733,6 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev)
|
|||
* driver and module entry point
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* Hardware specific file defines the PCI IDs table for that hardware module */
|
||||
static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
|
||||
|
||||
/* 5300 Series WiFi */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
|
||||
/* 5350 Series WiFi/WiMax */
|
||||
{IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
|
||||
|
||||
/* 5150 Series Wifi/WiMax */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
|
||||
|
||||
{IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
|
||||
|
||||
/* 6x00 Series */
|
||||
{IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
|
||||
|
||||
/* 6x05 Series */
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
|
||||
|
||||
/* 6x30 Series */
|
||||
{IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
|
||||
|
||||
/* 6x50 WiFi/WiMax Series */
|
||||
{IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
|
||||
|
||||
/* 6150 WiFi/WiMax Series */
|
||||
{IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0885, 0x1307, iwl6150_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0885, 0x1327, iwl6150_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0886, 0x1317, iwl6150_bg_cfg)},
|
||||
|
||||
/* 1000 Series WiFi */
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
|
||||
|
||||
/* 100 Series WiFi */
|
||||
{IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
|
||||
|
||||
/* 130 Series WiFi */
|
||||
{IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
|
||||
|
||||
/* 2x00 Series */
|
||||
{IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
|
||||
|
||||
/* 2x30 Series */
|
||||
{IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
|
||||
|
||||
/* 6x35 Series */
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
|
||||
|
||||
/* 105 Series */
|
||||
{IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)},
|
||||
|
||||
/* 135 Series */
|
||||
{IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)},
|
||||
|
||||
{0}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
|
||||
|
||||
static struct pci_driver iwl_driver = {
|
||||
.name = DRV_NAME,
|
||||
.id_table = iwl_hw_card_ids,
|
||||
.probe = iwl_pci_probe,
|
||||
.remove = __devexit_p(iwl_pci_remove),
|
||||
.driver.pm = IWL_PM_OPS,
|
||||
};
|
||||
|
||||
static int __init iwl_init(void)
|
||||
{
|
||||
|
||||
|
@ -4025,12 +3746,10 @@ static int __init iwl_init(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = pci_register_driver(&iwl_driver);
|
||||
if (ret) {
|
||||
pr_err("Unable to initialize PCI module\n");
|
||||
goto error_register;
|
||||
}
|
||||
ret = iwl_pci_register_driver();
|
||||
|
||||
if (ret)
|
||||
goto error_register;
|
||||
return ret;
|
||||
|
||||
error_register:
|
||||
|
@ -4040,7 +3759,7 @@ error_register:
|
|||
|
||||
static void __exit iwl_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&iwl_driver);
|
||||
iwl_pci_unregister_driver();
|
||||
iwlagn_rate_control_unregister();
|
||||
}
|
||||
|
||||
|
@ -4107,6 +3826,16 @@ module_param_named(led_mode, iwlagn_mod_params.led_mode, int, S_IRUGO);
|
|||
MODULE_PARM_DESC(led_mode, "0=system default, "
|
||||
"1=On(RF On)/Off(RF Off), 2=blinking (default: 0)");
|
||||
|
||||
module_param_named(power_save, iwlagn_mod_params.power_save,
|
||||
bool, S_IRUGO);
|
||||
MODULE_PARM_DESC(power_save,
|
||||
"enable WiFi power management (default: disable)");
|
||||
|
||||
module_param_named(power_level, iwlagn_mod_params.power_level,
|
||||
int, S_IRUGO);
|
||||
MODULE_PARM_DESC(power_level,
|
||||
"default power save level (range from 1 - 5, default: 1)");
|
||||
|
||||
/*
|
||||
* For now, keep using power level 1 instead of automatically
|
||||
* adjusting ...
|
||||
|
|
|
@ -125,7 +125,7 @@ irqreturn_t iwl_isr_ict(int irq, void *data);
|
|||
static inline void iwl_synchronize_irq(struct iwl_priv *priv)
|
||||
{
|
||||
/* wait to make sure we flush pending tasklet*/
|
||||
synchronize_irq(priv->pci_dev->irq);
|
||||
synchronize_irq(priv->bus.irq);
|
||||
tasklet_kill(&priv->irq_tasklet);
|
||||
}
|
||||
|
||||
|
@ -379,4 +379,8 @@ void iwl_testmode_cleanup(struct iwl_priv *priv)
|
|||
}
|
||||
#endif
|
||||
|
||||
int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
|
||||
struct iwl_cfg *cfg);
|
||||
void __devexit iwl_remove(struct iwl_priv * priv);
|
||||
|
||||
#endif /* __iwl_agn_h__ */
|
||||
|
|
|
@ -972,15 +972,26 @@ struct iwl_rem_sta_cmd {
|
|||
u8 reserved2[2];
|
||||
} __packed;
|
||||
|
||||
#define IWL_TX_FIFO_BK_MSK cpu_to_le32(BIT(0))
|
||||
#define IWL_TX_FIFO_BE_MSK cpu_to_le32(BIT(1))
|
||||
#define IWL_TX_FIFO_VI_MSK cpu_to_le32(BIT(2))
|
||||
#define IWL_TX_FIFO_VO_MSK cpu_to_le32(BIT(3))
|
||||
|
||||
/* WiFi queues mask */
|
||||
#define IWL_SCD_BK_MSK cpu_to_le32(BIT(0))
|
||||
#define IWL_SCD_BE_MSK cpu_to_le32(BIT(1))
|
||||
#define IWL_SCD_VI_MSK cpu_to_le32(BIT(2))
|
||||
#define IWL_SCD_VO_MSK cpu_to_le32(BIT(3))
|
||||
#define IWL_SCD_MGMT_MSK cpu_to_le32(BIT(3))
|
||||
|
||||
/* PAN queues mask */
|
||||
#define IWL_PAN_SCD_BK_MSK cpu_to_le32(BIT(4))
|
||||
#define IWL_PAN_SCD_BE_MSK cpu_to_le32(BIT(5))
|
||||
#define IWL_PAN_SCD_VI_MSK cpu_to_le32(BIT(6))
|
||||
#define IWL_PAN_SCD_VO_MSK cpu_to_le32(BIT(7))
|
||||
#define IWL_PAN_SCD_MGMT_MSK cpu_to_le32(BIT(7))
|
||||
#define IWL_PAN_SCD_MULTICAST_MSK cpu_to_le32(BIT(8))
|
||||
|
||||
#define IWL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
|
||||
|
||||
#define IWL_DROP_SINGLE 0
|
||||
#define IWL_DROP_SELECTED 1
|
||||
#define IWL_DROP_ALL 2
|
||||
#define IWL_DROP_ALL (BIT(IWL_RXON_CTX_BSS) | BIT(IWL_RXON_CTX_PAN))
|
||||
|
||||
/*
|
||||
* REPLY_TXFIFO_FLUSH = 0x1e(command and response)
|
||||
|
|
|
@ -209,10 +209,10 @@ int iwlcore_init_geos(struct iwl_priv *priv)
|
|||
|
||||
if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
|
||||
priv->cfg->sku & EEPROM_SKU_CAP_BAND_52GHZ) {
|
||||
char buf[32];
|
||||
priv->bus.ops->get_hw_id(&priv->bus, buf, sizeof(buf));
|
||||
IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
|
||||
"Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
|
||||
priv->pci_dev->device,
|
||||
priv->pci_dev->subsystem_device);
|
||||
"Please send your %s to maintainer.\n", buf);
|
||||
priv->cfg->sku &= ~EEPROM_SKU_CAP_BAND_52GHZ;
|
||||
}
|
||||
|
||||
|
@ -997,8 +997,6 @@ void iwl_apm_stop(struct iwl_priv *priv)
|
|||
int iwl_apm_init(struct iwl_priv *priv)
|
||||
{
|
||||
int ret = 0;
|
||||
u16 lctl;
|
||||
|
||||
IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
|
||||
|
||||
/*
|
||||
|
@ -1027,27 +1025,7 @@ int iwl_apm_init(struct iwl_priv *priv)
|
|||
iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
|
||||
CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
|
||||
|
||||
/*
|
||||
* HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
|
||||
* Check if BIOS (or OS) enabled L1-ASPM on this device.
|
||||
* If so (likely), disable L0S, so device moves directly L0->L1;
|
||||
* costs negligible amount of power savings.
|
||||
* If not (unlikely), enable L0S, so there is at least some
|
||||
* power savings, even without L1.
|
||||
*/
|
||||
lctl = iwl_pcie_link_ctl(priv);
|
||||
if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
|
||||
PCI_CFG_LINK_CTRL_VAL_L1_EN) {
|
||||
/* L1-ASPM enabled; disable(!) L0S */
|
||||
iwl_set_bit(priv, CSR_GIO_REG,
|
||||
CSR_GIO_REG_VAL_L0S_ENABLED);
|
||||
IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
|
||||
} else {
|
||||
/* L1-ASPM disabled; enable(!) L0S */
|
||||
iwl_clear_bit(priv, CSR_GIO_REG,
|
||||
CSR_GIO_REG_VAL_L0S_ENABLED);
|
||||
IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
|
||||
}
|
||||
priv->bus.ops->apm_config(&priv->bus);
|
||||
|
||||
/* Configure analog phase-lock-loop before activating to D0A */
|
||||
if (priv->cfg->base_params->pll_cfg_val)
|
||||
|
@ -1948,11 +1926,8 @@ __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
|
|||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
int iwl_pci_suspend(struct device *device)
|
||||
int iwl_suspend(struct iwl_priv *priv)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(device);
|
||||
struct iwl_priv *priv = pci_get_drvdata(pdev);
|
||||
|
||||
/*
|
||||
* This function is called when system goes into suspend state
|
||||
* mac80211 will call iwl_mac_stop() from the mac80211 suspend function
|
||||
|
@ -1965,18 +1940,10 @@ int iwl_pci_suspend(struct device *device)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int iwl_pci_resume(struct device *device)
|
||||
int iwl_resume(struct iwl_priv *priv)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(device);
|
||||
struct iwl_priv *priv = pci_get_drvdata(pdev);
|
||||
bool hw_rfkill = false;
|
||||
|
||||
/*
|
||||
* We disable the RETRY_TIMEOUT register (0x41) to keep
|
||||
* PCI Tx retries from interfering with C3 CPU state.
|
||||
*/
|
||||
pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
|
||||
|
||||
iwl_enable_interrupts(priv);
|
||||
|
||||
if (!(iwl_read32(priv, CSR_GP_CNTRL) &
|
||||
|
@ -1993,13 +1960,4 @@ int iwl_pci_resume(struct device *device)
|
|||
return 0;
|
||||
}
|
||||
|
||||
const struct dev_pm_ops iwl_pm_ops = {
|
||||
.suspend = iwl_pci_suspend,
|
||||
.resume = iwl_pci_resume,
|
||||
.freeze = iwl_pci_suspend,
|
||||
.thaw = iwl_pci_resume,
|
||||
.poweroff = iwl_pci_suspend,
|
||||
.restore = iwl_pci_resume,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
|
|
@ -76,11 +76,6 @@ struct iwl_cmd;
|
|||
#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
|
||||
#define DRV_AUTHOR "<ilw@linux.intel.com>"
|
||||
|
||||
#define IWL_PCI_DEVICE(dev, subdev, cfg) \
|
||||
.vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
|
||||
.subvendor = PCI_ANY_ID, .subdevice = (subdev), \
|
||||
.driver_data = (kernel_ulong_t)&(cfg)
|
||||
|
||||
#define TIME_UNIT 1024
|
||||
|
||||
#define IWL_CMD(x) case x: return #x
|
||||
|
@ -142,10 +137,6 @@ struct iwl_lib_ops {
|
|||
|
||||
/* temperature */
|
||||
struct iwl_temp_ops temp_ops;
|
||||
|
||||
int (*txfifo_flush)(struct iwl_priv *priv, u16 flush_control);
|
||||
void (*dev_txfifo_flush)(struct iwl_priv *priv, u16 flush_control);
|
||||
|
||||
};
|
||||
|
||||
/* NIC specific ops */
|
||||
|
@ -172,6 +163,8 @@ struct iwl_mod_params {
|
|||
bool bt_coex_active; /* def: true = enable bt coex */
|
||||
int led_mode; /* def: 0 = system default */
|
||||
bool no_sleep_autoadjust; /* def: true = disable autoadjust */
|
||||
bool power_save; /* def: false = disable power save */
|
||||
int power_level; /* def: 1 = power level */
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -479,36 +472,14 @@ int iwl_send_cmd_pdu_async(struct iwl_priv *priv, u8 id, u16 len,
|
|||
|
||||
int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
|
||||
|
||||
|
||||
/*****************************************************
|
||||
* PCI *
|
||||
*****************************************************/
|
||||
|
||||
static inline u16 iwl_pcie_link_ctl(struct iwl_priv *priv)
|
||||
{
|
||||
int pos;
|
||||
u16 pci_lnk_ctl;
|
||||
pos = pci_find_capability(priv->pci_dev, PCI_CAP_ID_EXP);
|
||||
pci_read_config_word(priv->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
|
||||
return pci_lnk_ctl;
|
||||
}
|
||||
|
||||
void iwl_bg_watchdog(unsigned long data);
|
||||
u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval);
|
||||
__le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
|
||||
u32 addon, u32 beacon_interval);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
int iwl_pci_suspend(struct device *device);
|
||||
int iwl_pci_resume(struct device *device);
|
||||
extern const struct dev_pm_ops iwl_pm_ops;
|
||||
|
||||
#define IWL_PM_OPS (&iwl_pm_ops)
|
||||
|
||||
#else /* !CONFIG_PM */
|
||||
|
||||
#define IWL_PM_OPS NULL
|
||||
|
||||
int iwl_suspend(struct iwl_priv *priv);
|
||||
int iwl_resume(struct iwl_priv *priv);
|
||||
#endif /* !CONFIG_PM */
|
||||
|
||||
/*****************************************************
|
||||
|
|
|
@ -32,10 +32,10 @@
|
|||
struct iwl_priv;
|
||||
extern u32 iwl_debug_level;
|
||||
|
||||
#define IWL_ERR(p, f, a...) dev_err(&((p)->pci_dev->dev), f, ## a)
|
||||
#define IWL_WARN(p, f, a...) dev_warn(&((p)->pci_dev->dev), f, ## a)
|
||||
#define IWL_INFO(p, f, a...) dev_info(&((p)->pci_dev->dev), f, ## a)
|
||||
#define IWL_CRIT(p, f, a...) dev_crit(&((p)->pci_dev->dev), f, ## a)
|
||||
#define IWL_ERR(p, f, a...) dev_err(p->bus.ops->get_dev(&p->bus), f, ## a)
|
||||
#define IWL_WARN(p, f, a...) dev_warn(p->bus.ops->get_dev(&p->bus), f, ## a)
|
||||
#define IWL_INFO(p, f, a...) dev_info(p->bus.ops->get_dev(&p->bus), f, ## a)
|
||||
#define IWL_CRIT(p, f, a...) dev_crit(p->bus.ops->get_dev(&p->bus), f, ## a)
|
||||
|
||||
#define iwl_print_hex_error(priv, p, len) \
|
||||
do { \
|
||||
|
|
|
@ -2493,7 +2493,7 @@ static ssize_t iwl_dbgfs_txfifo_flush_write(struct file *file,
|
|||
if (iwl_is_rfkill(priv))
|
||||
return -EFAULT;
|
||||
|
||||
priv->cfg->ops->lib->dev_txfifo_flush(priv, IWL_DROP_ALL);
|
||||
iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
@ -2693,8 +2693,7 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name)
|
|||
DEBUGFS_ADD_FILE(ucode_rx_stats, dir_debug, S_IRUSR);
|
||||
DEBUGFS_ADD_FILE(ucode_tx_stats, dir_debug, S_IRUSR);
|
||||
DEBUGFS_ADD_FILE(ucode_general_stats, dir_debug, S_IRUSR);
|
||||
if (priv->cfg->ops->lib->dev_txfifo_flush)
|
||||
DEBUGFS_ADD_FILE(txfifo_flush, dir_debug, S_IWUSR);
|
||||
DEBUGFS_ADD_FILE(txfifo_flush, dir_debug, S_IWUSR);
|
||||
DEBUGFS_ADD_FILE(protection_mode, dir_debug, S_IWUSR | S_IRUSR);
|
||||
|
||||
DEBUGFS_ADD_FILE(sensitivity, dir_debug, S_IRUSR);
|
||||
|
|
|
@ -48,6 +48,8 @@
|
|||
#include "iwl-agn-rs.h"
|
||||
#include "iwl-agn-tt.h"
|
||||
|
||||
#define DRV_NAME "iwlagn"
|
||||
|
||||
struct iwl_tx_queue;
|
||||
|
||||
/* CT-KILL constants */
|
||||
|
@ -1186,6 +1188,45 @@ struct iwl_testmode_trace {
|
|||
bool trace_enabled;
|
||||
};
|
||||
#endif
|
||||
|
||||
struct iwl_bus;
|
||||
|
||||
/**
|
||||
* struct iwl_bus_ops - bus specific operations
|
||||
|
||||
* @get_pm_support: must returns true if the bus can go to sleep
|
||||
* @apm_config: will be called during the config of the APM configuration
|
||||
* @set_drv_data: set the priv pointer to the bus layer
|
||||
* @get_dev: returns the device struct
|
||||
* @get_irq: returns the irq number
|
||||
* @get_hw_id: prints the hw_id in the provided buffer
|
||||
* @write8: write a byte to register at offset ofs
|
||||
* @write32: write a dword to register at offset ofs
|
||||
* @wread32: read a dword at register at offset ofs
|
||||
*/
|
||||
struct iwl_bus_ops {
|
||||
bool (*get_pm_support)(struct iwl_bus *bus);
|
||||
void (*apm_config)(struct iwl_bus *bus);
|
||||
void (*set_drv_data)(struct iwl_bus *bus, void *priv);
|
||||
struct device *(*get_dev)(const struct iwl_bus *bus);
|
||||
unsigned int (*get_irq)(const struct iwl_bus *bus);
|
||||
void (*get_hw_id)(struct iwl_bus *bus, char buf[], int buf_len);
|
||||
void (*write8)(struct iwl_bus *bus, u32 ofs, u8 val);
|
||||
void (*write32)(struct iwl_bus *bus, u32 ofs, u32 val);
|
||||
u32 (*read32)(struct iwl_bus *bus, u32 ofs);
|
||||
};
|
||||
|
||||
struct iwl_bus {
|
||||
/* pointer to bus specific struct */
|
||||
void *bus_specific;
|
||||
|
||||
/* Common data to all buses */
|
||||
struct iwl_priv *priv; /* driver's context */
|
||||
struct device *dev;
|
||||
struct iwl_bus_ops *ops;
|
||||
unsigned int irq;
|
||||
};
|
||||
|
||||
struct iwl_priv {
|
||||
|
||||
/* ieee device used by generic ieee processing code */
|
||||
|
@ -1253,17 +1294,14 @@ struct iwl_priv {
|
|||
spinlock_t reg_lock; /* protect hw register access */
|
||||
struct mutex mutex;
|
||||
|
||||
/* basic pci-network driver stuff */
|
||||
struct pci_dev *pci_dev;
|
||||
|
||||
/* pci hardware address support */
|
||||
void __iomem *hw_base;
|
||||
struct iwl_bus bus; /* bus specific data */
|
||||
|
||||
/* microcode/device supports multiple contexts */
|
||||
u8 valid_contexts;
|
||||
|
||||
/* command queue number */
|
||||
u8 cmd_queue;
|
||||
u8 last_sync_cmd_id;
|
||||
|
||||
/* max number of station keys */
|
||||
u8 sta_key_max_num;
|
||||
|
|
|
@ -834,3 +834,28 @@ const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
|
|||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void iwl_rf_config(struct iwl_priv *priv)
|
||||
{
|
||||
u16 radio_cfg;
|
||||
|
||||
radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
|
||||
|
||||
/* write radio config values to register */
|
||||
if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
|
||||
iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
|
||||
EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
|
||||
EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
|
||||
EEPROM_RF_CFG_DASH_MSK(radio_cfg));
|
||||
IWL_INFO(priv, "Radio type=0x%x-0x%x-0x%x\n",
|
||||
EEPROM_RF_CFG_TYPE_MSK(radio_cfg),
|
||||
EEPROM_RF_CFG_STEP_MSK(radio_cfg),
|
||||
EEPROM_RF_CFG_DASH_MSK(radio_cfg));
|
||||
} else
|
||||
WARN_ON(1);
|
||||
|
||||
/* set CSR_HW_CONFIG_REG for uCode use */
|
||||
iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
|
||||
CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
|
||||
CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
|
||||
}
|
||||
|
|
|
@ -268,13 +268,13 @@ extern const u8 iwl_eeprom_band_1[14];
|
|||
|
||||
/* General */
|
||||
#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
|
||||
#define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */
|
||||
#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
|
||||
#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
|
||||
#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
|
||||
#define EEPROM_VERSION (2*0x44) /* 2 bytes */
|
||||
#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
|
||||
#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
|
||||
#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
|
||||
#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
|
||||
#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
|
||||
|
||||
|
@ -309,5 +309,6 @@ void iwl_free_channel_map(struct iwl_priv *priv);
|
|||
const struct iwl_channel_info *iwl_get_channel_info(
|
||||
const struct iwl_priv *priv,
|
||||
enum ieee80211_band band, u16 channel);
|
||||
void iwl_rf_config(struct iwl_priv *priv);
|
||||
|
||||
#endif /* __iwl_eeprom_h__ */
|
||||
|
|
|
@ -181,7 +181,16 @@ int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|||
IWL_DEBUG_INFO(priv, "Attempting to send sync command %s\n",
|
||||
get_cmd_string(cmd->id));
|
||||
|
||||
set_bit(STATUS_HCMD_ACTIVE, &priv->status);
|
||||
if (test_and_set_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
|
||||
IWL_ERR(priv, "STATUS_HCMD_ACTIVE already set while sending %s"
|
||||
". Previous SYNC cmdn is %s\n",
|
||||
get_cmd_string(cmd->id),
|
||||
get_cmd_string(priv->last_sync_cmd_id));
|
||||
WARN_ON(1);
|
||||
} else {
|
||||
priv->last_sync_cmd_id = cmd->id;
|
||||
}
|
||||
|
||||
IWL_DEBUG_INFO(priv, "Setting HCMD_ACTIVE for command %s\n",
|
||||
get_cmd_string(cmd->id));
|
||||
|
||||
|
|
|
@ -38,18 +38,18 @@
|
|||
static inline void iwl_write8(struct iwl_priv *priv, u32 ofs, u8 val)
|
||||
{
|
||||
trace_iwlwifi_dev_iowrite8(priv, ofs, val);
|
||||
iowrite8(val, priv->hw_base + ofs);
|
||||
priv->bus.ops->write8(&priv->bus, ofs, val);
|
||||
}
|
||||
|
||||
static inline void iwl_write32(struct iwl_priv *priv, u32 ofs, u32 val)
|
||||
{
|
||||
trace_iwlwifi_dev_iowrite32(priv, ofs, val);
|
||||
iowrite32(val, priv->hw_base + ofs);
|
||||
priv->bus.ops->write32(&priv->bus, ofs, val);
|
||||
}
|
||||
|
||||
static inline u32 iwl_read32(struct iwl_priv *priv, u32 ofs)
|
||||
{
|
||||
u32 val = ioread32(priv->hw_base + ofs);
|
||||
u32 val = priv->bus.ops->read32(&priv->bus, ofs);
|
||||
trace_iwlwifi_dev_ioread32(priv, ofs, val);
|
||||
return val;
|
||||
}
|
||||
|
|
|
@ -28,8 +28,6 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/netdevice.h>
|
||||
|
@ -204,7 +202,8 @@ void iwl_leds_init(struct iwl_priv *priv)
|
|||
break;
|
||||
}
|
||||
|
||||
ret = led_classdev_register(&priv->pci_dev->dev, &priv->led);
|
||||
ret = led_classdev_register(priv->bus.dev,
|
||||
&priv->led);
|
||||
if (ret) {
|
||||
kfree(priv->led.name);
|
||||
return;
|
||||
|
|
|
@ -0,0 +1,571 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
|
||||
* USA
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.GPL.
|
||||
*
|
||||
* Contact Information:
|
||||
* Intel Linux Wireless <ilw@linux.intel.com>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pci-aspm.h>
|
||||
|
||||
#include "iwl-pci.h"
|
||||
#include "iwl-agn.h"
|
||||
#include "iwl-core.h"
|
||||
#include "iwl-io.h"
|
||||
|
||||
/* PCI registers */
|
||||
#define PCI_CFG_RETRY_TIMEOUT 0x041
|
||||
#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
|
||||
#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
|
||||
|
||||
struct iwl_pci_bus {
|
||||
/* basic pci-network driver stuff */
|
||||
struct pci_dev *pci_dev;
|
||||
|
||||
/* pci hardware address support */
|
||||
void __iomem *hw_base;
|
||||
};
|
||||
|
||||
#define IWL_BUS_GET_PCI_BUS(_iwl_bus) \
|
||||
((struct iwl_pci_bus *) ((_iwl_bus)->bus_specific))
|
||||
|
||||
#define IWL_BUS_GET_PCI_DEV(_iwl_bus) \
|
||||
((IWL_BUS_GET_PCI_BUS(_iwl_bus))->pci_dev)
|
||||
|
||||
static u16 iwl_pciexp_link_ctrl(struct iwl_bus *bus)
|
||||
{
|
||||
int pos;
|
||||
u16 pci_lnk_ctl;
|
||||
struct pci_dev *pci_dev = IWL_BUS_GET_PCI_DEV(bus);
|
||||
|
||||
pos = pci_find_capability(pci_dev, PCI_CAP_ID_EXP);
|
||||
pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
|
||||
return pci_lnk_ctl;
|
||||
}
|
||||
|
||||
static bool iwl_pci_is_pm_supported(struct iwl_bus *bus)
|
||||
{
|
||||
u16 lctl = iwl_pciexp_link_ctrl(bus);
|
||||
|
||||
return !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
|
||||
}
|
||||
|
||||
static void iwl_pci_apm_config(struct iwl_bus *bus)
|
||||
{
|
||||
/*
|
||||
* HW bug W/A for instability in PCIe bus L0S->L1 transition.
|
||||
* Check if BIOS (or OS) enabled L1-ASPM on this device.
|
||||
* If so (likely), disable L0S, so device moves directly L0->L1;
|
||||
* costs negligible amount of power savings.
|
||||
* If not (unlikely), enable L0S, so there is at least some
|
||||
* power savings, even without L1.
|
||||
*/
|
||||
u16 lctl = iwl_pciexp_link_ctrl(bus);
|
||||
|
||||
if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
|
||||
PCI_CFG_LINK_CTRL_VAL_L1_EN) {
|
||||
/* L1-ASPM enabled; disable(!) L0S */
|
||||
iwl_set_bit(bus->priv, CSR_GIO_REG,
|
||||
CSR_GIO_REG_VAL_L0S_ENABLED);
|
||||
IWL_DEBUG_POWER(bus->priv, "L1 Enabled; Disabling L0S\n");
|
||||
} else {
|
||||
/* L1-ASPM disabled; enable(!) L0S */
|
||||
iwl_clear_bit(bus->priv, CSR_GIO_REG,
|
||||
CSR_GIO_REG_VAL_L0S_ENABLED);
|
||||
IWL_DEBUG_POWER(bus->priv, "L1 Disabled; Enabling L0S\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void iwl_pci_set_drv_data(struct iwl_bus *bus, void *drv_priv)
|
||||
{
|
||||
pci_set_drvdata(IWL_BUS_GET_PCI_DEV(bus), drv_priv);
|
||||
}
|
||||
|
||||
static struct device *iwl_pci_get_dev(const struct iwl_bus *bus)
|
||||
{
|
||||
return &(IWL_BUS_GET_PCI_DEV(bus)->dev);
|
||||
}
|
||||
|
||||
static unsigned int iwl_pci_get_irq(const struct iwl_bus *bus)
|
||||
{
|
||||
return IWL_BUS_GET_PCI_DEV(bus)->irq;
|
||||
}
|
||||
|
||||
static void iwl_pci_get_hw_id(struct iwl_bus *bus, char buf[],
|
||||
int buf_len)
|
||||
{
|
||||
struct pci_dev *pci_dev = IWL_BUS_GET_PCI_DEV(bus);
|
||||
|
||||
snprintf(buf, buf_len, "PCI ID: 0x%04X:0x%04X", pci_dev->device,
|
||||
pci_dev->subsystem_device);
|
||||
}
|
||||
|
||||
static void iwl_pci_write8(struct iwl_bus *bus, u32 ofs, u8 val)
|
||||
{
|
||||
iowrite8(val, IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
|
||||
}
|
||||
|
||||
static void iwl_pci_write32(struct iwl_bus *bus, u32 ofs, u32 val)
|
||||
{
|
||||
iowrite32(val, IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
|
||||
}
|
||||
|
||||
static u32 iwl_pci_read32(struct iwl_bus *bus, u32 ofs)
|
||||
{
|
||||
u32 val = ioread32(IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
|
||||
return val;
|
||||
}
|
||||
|
||||
static struct iwl_bus_ops pci_ops = {
|
||||
.get_pm_support = iwl_pci_is_pm_supported,
|
||||
.apm_config = iwl_pci_apm_config,
|
||||
.set_drv_data = iwl_pci_set_drv_data,
|
||||
.get_dev = iwl_pci_get_dev,
|
||||
.get_irq = iwl_pci_get_irq,
|
||||
.get_hw_id = iwl_pci_get_hw_id,
|
||||
.write8 = iwl_pci_write8,
|
||||
.write32 = iwl_pci_write32,
|
||||
.read32 = iwl_pci_read32,
|
||||
};
|
||||
|
||||
#define IWL_PCI_DEVICE(dev, subdev, cfg) \
|
||||
.vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
|
||||
.subvendor = PCI_ANY_ID, .subdevice = (subdev), \
|
||||
.driver_data = (kernel_ulong_t)&(cfg)
|
||||
|
||||
/* Hardware specific file defines the PCI IDs table for that hardware module */
|
||||
static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
|
||||
|
||||
/* 5300 Series WiFi */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
|
||||
|
||||
/* 5350 Series WiFi/WiMax */
|
||||
{IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
|
||||
|
||||
/* 5150 Series Wifi/WiMax */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
|
||||
|
||||
{IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
|
||||
{IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
|
||||
|
||||
/* 6x00 Series */
|
||||
{IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
|
||||
|
||||
/* 6x05 Series */
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
|
||||
|
||||
/* 6x30 Series */
|
||||
{IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
|
||||
|
||||
/* 6x50 WiFi/WiMax Series */
|
||||
{IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
|
||||
|
||||
/* 6150 WiFi/WiMax Series */
|
||||
{IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0885, 0x1307, iwl6150_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0885, 0x1327, iwl6150_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0886, 0x1317, iwl6150_bg_cfg)},
|
||||
|
||||
/* 1000 Series WiFi */
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
|
||||
|
||||
/* 100 Series WiFi */
|
||||
{IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
|
||||
|
||||
/* 130 Series WiFi */
|
||||
{IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
|
||||
|
||||
/* 2x00 Series */
|
||||
{IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
|
||||
|
||||
/* 2x30 Series */
|
||||
{IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
|
||||
|
||||
/* 6x35 Series */
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
|
||||
|
||||
/* 105 Series */
|
||||
{IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)},
|
||||
|
||||
/* 135 Series */
|
||||
{IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)},
|
||||
{IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)},
|
||||
|
||||
{0}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
|
||||
|
||||
static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
|
||||
struct iwl_pci_bus *bus;
|
||||
u8 rev_id;
|
||||
u16 pci_cmd;
|
||||
int err;
|
||||
|
||||
bus = kzalloc(sizeof(*bus), GFP_KERNEL);
|
||||
if (!bus) {
|
||||
pr_err("Couldn't allocate iwl_pci_bus");
|
||||
err = -ENOMEM;
|
||||
goto out_no_pci;
|
||||
}
|
||||
|
||||
bus->pci_dev = pdev;
|
||||
|
||||
/* W/A - seems to solve weird behavior. We need to remove this if we
|
||||
* don't want to stay in L1 all the time. This wastes a lot of power */
|
||||
pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
|
||||
PCIE_LINK_STATE_CLKPM);
|
||||
|
||||
if (pci_enable_device(pdev)) {
|
||||
err = -ENODEV;
|
||||
goto out_no_pci;
|
||||
}
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
|
||||
if (!err)
|
||||
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
|
||||
if (err) {
|
||||
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (!err)
|
||||
err = pci_set_consistent_dma_mask(pdev,
|
||||
DMA_BIT_MASK(32));
|
||||
/* both attempts failed: */
|
||||
if (err) {
|
||||
pr_err("No suitable DMA available.\n");
|
||||
goto out_pci_disable_device;
|
||||
}
|
||||
}
|
||||
|
||||
err = pci_request_regions(pdev, DRV_NAME);
|
||||
if (err) {
|
||||
pr_err("pci_request_regions failed");
|
||||
goto out_pci_disable_device;
|
||||
}
|
||||
|
||||
bus->hw_base = pci_iomap(pdev, 0, 0);
|
||||
if (!bus->hw_base) {
|
||||
pr_err("pci_iomap failed");
|
||||
err = -ENODEV;
|
||||
goto out_pci_release_regions;
|
||||
}
|
||||
|
||||
pr_info("pci_resource_len = 0x%08llx\n",
|
||||
(unsigned long long) pci_resource_len(pdev, 0));
|
||||
pr_info("pci_resource_base = %p\n", bus->hw_base);
|
||||
|
||||
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
|
||||
pr_info("HW Revision ID = 0x%X\n", rev_id);
|
||||
|
||||
/* We disable the RETRY_TIMEOUT register (0x41) to keep
|
||||
* PCI Tx retries from interfering with C3 CPU state */
|
||||
pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
|
||||
|
||||
err = pci_enable_msi(pdev);
|
||||
if (err) {
|
||||
pr_err("pci_enable_msi failed");
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
/* TODO: Move this away, not needed if not MSI */
|
||||
/* enable rfkill interrupt: hw bug w/a */
|
||||
pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
|
||||
if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
|
||||
pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
|
||||
pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
|
||||
}
|
||||
|
||||
err = iwl_probe((void *) bus, &pci_ops, cfg);
|
||||
if (err)
|
||||
goto out_disable_msi;
|
||||
return 0;
|
||||
|
||||
out_disable_msi:
|
||||
pci_disable_msi(pdev);
|
||||
out_iounmap:
|
||||
pci_iounmap(pdev, bus->hw_base);
|
||||
out_pci_release_regions:
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
pci_release_regions(pdev);
|
||||
out_pci_disable_device:
|
||||
pci_disable_device(pdev);
|
||||
out_no_pci:
|
||||
kfree(bus);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void iwl_pci_down(void *bus)
|
||||
{
|
||||
struct iwl_pci_bus *pci_bus = (struct iwl_pci_bus *) bus;
|
||||
|
||||
pci_disable_msi(pci_bus->pci_dev);
|
||||
pci_iounmap(pci_bus->pci_dev, pci_bus->hw_base);
|
||||
pci_release_regions(pci_bus->pci_dev);
|
||||
pci_disable_device(pci_bus->pci_dev);
|
||||
pci_set_drvdata(pci_bus->pci_dev, NULL);
|
||||
|
||||
kfree(pci_bus);
|
||||
}
|
||||
|
||||
static void __devexit iwl_pci_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct iwl_priv *priv = pci_get_drvdata(pdev);
|
||||
|
||||
/* This can happen if probe failed */
|
||||
if (unlikely(!priv))
|
||||
return;
|
||||
|
||||
iwl_remove(priv);
|
||||
|
||||
iwl_pci_down(IWL_BUS_GET_PCI_BUS(&priv->bus));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static int iwl_pci_suspend(struct device *device)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(device);
|
||||
struct iwl_priv *priv = pci_get_drvdata(pdev);
|
||||
|
||||
return iwl_suspend(priv);
|
||||
}
|
||||
|
||||
static int iwl_pci_resume(struct device *device)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(device);
|
||||
struct iwl_priv *priv = pci_get_drvdata(pdev);
|
||||
|
||||
/*
|
||||
* We disable the RETRY_TIMEOUT register (0x41) to keep
|
||||
* PCI Tx retries from interfering with C3 CPU state.
|
||||
*/
|
||||
pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
|
||||
|
||||
return iwl_resume(priv);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops iwl_dev_pm_ops = {
|
||||
.suspend = iwl_pci_suspend,
|
||||
.resume = iwl_pci_resume,
|
||||
.freeze = iwl_pci_suspend,
|
||||
.thaw = iwl_pci_resume,
|
||||
.poweroff = iwl_pci_suspend,
|
||||
.restore = iwl_pci_resume,
|
||||
};
|
||||
|
||||
#define IWL_PM_OPS (&iwl_dev_pm_ops)
|
||||
|
||||
#else
|
||||
|
||||
#define IWL_PM_OPS NULL
|
||||
|
||||
#endif
|
||||
|
||||
static struct pci_driver iwl_pci_driver = {
|
||||
.name = DRV_NAME,
|
||||
.id_table = iwl_hw_card_ids,
|
||||
.probe = iwl_pci_probe,
|
||||
.remove = __devexit_p(iwl_pci_remove),
|
||||
.driver.pm = IWL_PM_OPS,
|
||||
};
|
||||
|
||||
int __must_check iwl_pci_register_driver(void)
|
||||
{
|
||||
int ret;
|
||||
ret = pci_register_driver(&iwl_pci_driver);
|
||||
if (ret)
|
||||
pr_err("Unable to initialize PCI module\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void iwl_pci_unregister_driver(void)
|
||||
{
|
||||
pci_unregister_driver(&iwl_pci_driver);
|
||||
}
|
|
@ -0,0 +1,69 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
|
||||
* USA
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called LICENSE.GPL.
|
||||
*
|
||||
* Contact Information:
|
||||
* Intel Linux Wireless <ilw@linux.intel.com>
|
||||
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __iwl_pci_h__
|
||||
#define __iwl_pci_h__
|
||||
|
||||
int __must_check iwl_pci_register_driver(void);
|
||||
void iwl_pci_unregister_driver(void);
|
||||
|
||||
#endif
|
|
@ -245,7 +245,7 @@ static void iwl_static_sleep_cmd(struct iwl_priv *priv,
|
|||
}
|
||||
}
|
||||
|
||||
if (priv->power_data.pci_pm)
|
||||
if (priv->power_data.bus_pm)
|
||||
cmd->flags |= IWL_POWER_PCI_PM_MSK;
|
||||
else
|
||||
cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
|
||||
|
@ -260,7 +260,7 @@ static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
|
|||
{
|
||||
memset(cmd, 0, sizeof(*cmd));
|
||||
|
||||
if (priv->power_data.pci_pm)
|
||||
if (priv->power_data.bus_pm)
|
||||
cmd->flags |= IWL_POWER_PCI_PM_MSK;
|
||||
|
||||
IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
|
||||
|
@ -296,7 +296,7 @@ static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
|
|||
cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
|
||||
IWL_POWER_FAST_PD; /* no use seeing frames for others */
|
||||
|
||||
if (priv->power_data.pci_pm)
|
||||
if (priv->power_data.bus_pm)
|
||||
cmd->flags |= IWL_POWER_PCI_PM_MSK;
|
||||
|
||||
if (priv->cfg->base_params->shadow_reg_enable)
|
||||
|
@ -358,9 +358,15 @@ static void iwl_power_build_cmd(struct iwl_priv *priv,
|
|||
iwl_static_sleep_cmd(priv, cmd,
|
||||
priv->power_data.debug_sleep_level_override,
|
||||
dtimper);
|
||||
else if (iwlagn_mod_params.no_sleep_autoadjust)
|
||||
iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper);
|
||||
else
|
||||
else if (iwlagn_mod_params.no_sleep_autoadjust) {
|
||||
if (iwlagn_mod_params.power_level > IWL_POWER_INDEX_1 &&
|
||||
iwlagn_mod_params.power_level <= IWL_POWER_INDEX_5)
|
||||
iwl_static_sleep_cmd(priv, cmd,
|
||||
iwlagn_mod_params.power_level, dtimper);
|
||||
else
|
||||
iwl_static_sleep_cmd(priv, cmd,
|
||||
IWL_POWER_INDEX_1, dtimper);
|
||||
} else
|
||||
iwl_power_fill_sleep_cmd(priv, cmd,
|
||||
priv->hw->conf.dynamic_ps_timeout,
|
||||
priv->hw->conf.max_sleep_period);
|
||||
|
@ -425,9 +431,7 @@ int iwl_power_update_mode(struct iwl_priv *priv, bool force)
|
|||
/* initialize to default */
|
||||
void iwl_power_initialize(struct iwl_priv *priv)
|
||||
{
|
||||
u16 lctl = iwl_pcie_link_ctl(priv);
|
||||
|
||||
priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
|
||||
priv->power_data.bus_pm = priv->bus.ops->get_pm_support(&priv->bus);
|
||||
|
||||
priv->power_data.debug_sleep_level_override = -1;
|
||||
|
||||
|
|
|
@ -43,7 +43,7 @@ struct iwl_power_mgr {
|
|||
struct iwl_powertable_cmd sleep_cmd;
|
||||
struct iwl_powertable_cmd sleep_cmd_next;
|
||||
int debug_sleep_level_override;
|
||||
bool pci_pm;
|
||||
bool bus_pm;
|
||||
};
|
||||
|
||||
int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
|
||||
|
|
|
@ -182,7 +182,7 @@ void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q
|
|||
int iwl_rx_queue_alloc(struct iwl_priv *priv)
|
||||
{
|
||||
struct iwl_rx_queue *rxq = &priv->rxq;
|
||||
struct device *dev = &priv->pci_dev->dev;
|
||||
struct device *dev = priv->bus.dev;
|
||||
int i;
|
||||
|
||||
spin_lock_init(&rxq->lock);
|
||||
|
@ -213,7 +213,7 @@ int iwl_rx_queue_alloc(struct iwl_priv *priv)
|
|||
return 0;
|
||||
|
||||
err_rb:
|
||||
dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
|
||||
dma_free_coherent(dev, 4 * RX_QUEUE_SIZE, rxq->bd,
|
||||
rxq->bd_dma);
|
||||
err_bd:
|
||||
return -ENOMEM;
|
||||
|
|
|
@ -180,7 +180,7 @@ void iwl_testmode_init(struct iwl_priv *priv)
|
|||
|
||||
static void iwl_trace_cleanup(struct iwl_priv *priv)
|
||||
{
|
||||
struct device *dev = &priv->pci_dev->dev;
|
||||
struct device *dev = priv->bus.dev;
|
||||
|
||||
if (priv->testmode_trace.trace_enabled) {
|
||||
if (priv->testmode_trace.cpu_addr &&
|
||||
|
@ -484,7 +484,7 @@ static int iwl_testmode_trace(struct ieee80211_hw *hw, struct nlattr **tb)
|
|||
struct iwl_priv *priv = hw->priv;
|
||||
struct sk_buff *skb;
|
||||
int status = 0;
|
||||
struct device *dev = &priv->pci_dev->dev;
|
||||
struct device *dev = priv->bus.dev;
|
||||
|
||||
switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) {
|
||||
case IWL_TM_CMD_APP2DEV_BEGIN_TRACE:
|
||||
|
|
|
@ -128,7 +128,6 @@ static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
|
|||
static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
|
||||
struct iwl_tfd *tfd)
|
||||
{
|
||||
struct pci_dev *dev = priv->pci_dev;
|
||||
int i;
|
||||
int num_tbs;
|
||||
|
||||
|
@ -143,15 +142,15 @@ static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
|
|||
|
||||
/* Unmap tx_cmd */
|
||||
if (num_tbs)
|
||||
pci_unmap_single(dev,
|
||||
dma_unmap_single(priv->bus.dev,
|
||||
dma_unmap_addr(meta, mapping),
|
||||
dma_unmap_len(meta, len),
|
||||
PCI_DMA_BIDIRECTIONAL);
|
||||
DMA_BIDIRECTIONAL);
|
||||
|
||||
/* Unmap chunks, if any. */
|
||||
for (i = 1; i < num_tbs; i++)
|
||||
pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
|
||||
iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
|
||||
dma_unmap_single(priv->bus.dev, iwl_tfd_tb_get_addr(tfd, i),
|
||||
iwl_tfd_tb_get_len(tfd, i), DMA_TO_DEVICE);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -266,7 +265,7 @@ void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
|
|||
void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
|
||||
{
|
||||
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
||||
struct device *dev = &priv->pci_dev->dev;
|
||||
struct device *dev = priv->bus.dev;
|
||||
int i;
|
||||
|
||||
iwl_tx_queue_unmap(priv, txq_id);
|
||||
|
@ -310,10 +309,10 @@ void iwl_cmd_queue_unmap(struct iwl_priv *priv)
|
|||
i = get_cmd_index(q, q->read_ptr);
|
||||
|
||||
if (txq->meta[i].flags & CMD_MAPPED) {
|
||||
pci_unmap_single(priv->pci_dev,
|
||||
dma_unmap_single(priv->bus.dev,
|
||||
dma_unmap_addr(&txq->meta[i], mapping),
|
||||
dma_unmap_len(&txq->meta[i], len),
|
||||
PCI_DMA_BIDIRECTIONAL);
|
||||
DMA_BIDIRECTIONAL);
|
||||
txq->meta[i].flags = 0;
|
||||
}
|
||||
|
||||
|
@ -332,7 +331,7 @@ void iwl_cmd_queue_unmap(struct iwl_priv *priv)
|
|||
void iwl_cmd_queue_free(struct iwl_priv *priv)
|
||||
{
|
||||
struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
|
||||
struct device *dev = &priv->pci_dev->dev;
|
||||
struct device *dev = priv->bus.dev;
|
||||
int i;
|
||||
|
||||
iwl_cmd_queue_unmap(priv);
|
||||
|
@ -434,7 +433,7 @@ static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
|
|||
static int iwl_tx_queue_alloc(struct iwl_priv *priv,
|
||||
struct iwl_tx_queue *txq, u32 id)
|
||||
{
|
||||
struct device *dev = &priv->pci_dev->dev;
|
||||
struct device *dev = priv->bus.dev;
|
||||
size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
|
||||
|
||||
/* Driver private data, only for Tx (not command) queues,
|
||||
|
@ -456,7 +455,7 @@ static int iwl_tx_queue_alloc(struct iwl_priv *priv,
|
|||
txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
|
||||
GFP_KERNEL);
|
||||
if (!txq->tfds) {
|
||||
IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
|
||||
IWL_ERR(priv, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
|
||||
goto error;
|
||||
}
|
||||
txq->q.id = id;
|
||||
|
@ -677,9 +676,9 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|||
le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
|
||||
q->write_ptr, idx, priv->cmd_queue);
|
||||
|
||||
phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
|
||||
copy_size, PCI_DMA_BIDIRECTIONAL);
|
||||
if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) {
|
||||
phys_addr = dma_map_single(priv->bus.dev, &out_cmd->hdr, copy_size,
|
||||
DMA_BIDIRECTIONAL);
|
||||
if (unlikely(dma_mapping_error(priv->bus.dev, phys_addr))) {
|
||||
idx = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
@ -699,9 +698,9 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
|||
continue;
|
||||
if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
|
||||
continue;
|
||||
phys_addr = pci_map_single(priv->pci_dev, (void *)cmd->data[i],
|
||||
cmd->len[i], PCI_DMA_TODEVICE);
|
||||
if (pci_dma_mapping_error(priv->pci_dev, phys_addr)) {
|
||||
phys_addr = dma_map_single(priv->bus.dev, (void *)cmd->data[i],
|
||||
cmd->len[i], DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(priv->bus.dev, phys_addr)) {
|
||||
iwlagn_unmap_tfd(priv, out_meta,
|
||||
&txq->tfds[q->write_ptr]);
|
||||
idx = -ENOMEM;
|
||||
|
|
Loading…
Reference in New Issue