drm/nouveau/falcon: remove object accessor functions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
a47474261e
commit
63902181a7
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@ -76,6 +76,4 @@ void nvkm_falcon_intr(struct nvkm_subdev *subdev);
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#define _nvkm_falcon_dtor _nvkm_engine_dtor
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int _nvkm_falcon_init(struct nvkm_object *);
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int _nvkm_falcon_fini(struct nvkm_object *, bool);
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u32 _nvkm_falcon_rd32(struct nvkm_object *, u64);
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void _nvkm_falcon_wr32(struct nvkm_object *, u64, u32);
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#endif
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@ -75,13 +75,16 @@ static int
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gf100_ce_init(struct nvkm_object *object)
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{
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struct nvkm_falcon *ce = (void *)object;
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struct nvkm_device *device = ce->engine.subdev.device;
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const int idx = nv_engidx(&ce->engine) - NVDEV_ENGINE_CE0;
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u32 base = idx * 0x1000;
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int ret;
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ret = nvkm_falcon_init(ce);
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if (ret)
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return ret;
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nv_wo32(ce, 0x084, nv_engidx(&ce->engine) - NVDEV_ENGINE_CE0);
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nvkm_wr32(device, 0x104084 + base, idx);
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return 0;
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}
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@ -143,8 +146,6 @@ gf100_ce0_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = gf100_ce_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -156,7 +157,5 @@ gf100_ce1_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = gf100_ce_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -72,19 +72,21 @@ gt215_ce_isr_error_name[] = {
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void
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gt215_ce_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_fifo *fifo = nvkm_fifo(subdev);
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struct nvkm_engine *engine = nv_engine(subdev);
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struct nvkm_falcon *falcon = (void *)subdev;
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struct nvkm_falcon *ce = (void *)subdev;
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struct nvkm_engine *engine = &ce->engine;
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struct nvkm_device *device = engine->subdev.device;
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struct nvkm_fifo *fifo = device->fifo;
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struct nvkm_object *engctx;
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const struct nvkm_enum *en;
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u32 dispatch = nv_ro32(falcon, 0x01c);
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u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16);
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u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff;
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u32 ssta = nv_ro32(falcon, 0x040) & 0x0000ffff;
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u32 addr = nv_ro32(falcon, 0x040) >> 16;
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const u32 base = (nv_subidx(subdev) - NVDEV_ENGINE_CE0) * 0x1000;
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u32 dispatch = nvkm_rd32(device, 0x10401c + base);
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u32 stat = nvkm_rd32(device, 0x104008 + base) & dispatch & ~(dispatch >> 16);
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u64 inst = nvkm_rd32(device, 0x104050 + base) & 0x3fffffff;
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u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff;
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u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16;
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u32 mthd = (addr & 0x07ff) << 2;
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u32 subc = (addr & 0x3800) >> 11;
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u32 data = nv_ro32(falcon, 0x044);
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u32 data = nvkm_rd32(device, 0x104044 + base);
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int chid;
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engctx = nvkm_engctx_get(engine, inst);
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@ -97,13 +99,13 @@ gt215_ce_intr(struct nvkm_subdev *subdev)
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"mthd %04x data %08x\n",
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ssta, en ? en->name : "", chid, inst << 12,
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nvkm_client_name(engctx), subc, mthd, data);
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nv_wo32(falcon, 0x004, 0x00000040);
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nvkm_wr32(device, 0x104004 + base, 0x00000040);
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stat &= ~0x00000040;
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}
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if (stat) {
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nvkm_error(subdev, "intr %08x\n", stat);
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nv_wo32(falcon, 0x004, stat);
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nvkm_wr32(device, 0x104004 + base, stat);
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}
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nvkm_engctx_put(engctx);
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@ -143,7 +145,5 @@ gt215_ce_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = _nvkm_falcon_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -27,35 +27,23 @@ void
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nvkm_falcon_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_falcon *falcon = (void *)subdev;
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u32 dispatch = nv_ro32(falcon, 0x01c);
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u32 intr = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16);
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struct nvkm_device *device = falcon->engine.subdev.device;
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const u32 base = falcon->addr;
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u32 dispatch = nvkm_rd32(device, base + 0x01c);
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u32 intr = nvkm_rd32(device, base + 0x008) & dispatch & ~(dispatch >> 16);
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if (intr & 0x00000010) {
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nvkm_debug(subdev, "ucode halted\n");
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nv_wo32(falcon, 0x004, 0x00000010);
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nvkm_wr32(device, base + 0x004, 0x00000010);
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intr &= ~0x00000010;
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}
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if (intr) {
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nvkm_error(subdev, "intr %08x\n", intr);
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nv_wo32(falcon, 0x004, intr);
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nvkm_wr32(device, base + 0x004, intr);
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}
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}
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u32
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_nvkm_falcon_rd32(struct nvkm_object *object, u64 addr)
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{
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struct nvkm_falcon *falcon = (void *)object;
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return nvkm_rd32(falcon->engine.subdev.device, falcon->addr + addr);
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}
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void
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_nvkm_falcon_wr32(struct nvkm_object *object, u64 addr, u32 data)
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{
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struct nvkm_falcon *falcon = (void *)object;
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nvkm_wr32(falcon->engine.subdev.device, falcon->addr + addr, data);
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}
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static void *
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vmemdup(const void *src, size_t len)
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{
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@ -74,6 +62,7 @@ _nvkm_falcon_init(struct nvkm_object *object)
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struct nvkm_device *device = subdev->device;
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const struct firmware *fw;
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char name[32] = "internal";
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const u32 base = falcon->addr;
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int ret, i;
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u32 caps;
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@ -87,12 +76,12 @@ _nvkm_falcon_init(struct nvkm_object *object)
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falcon->version = 0;
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falcon->secret = (falcon->addr == 0x087000) ? 1 : 0;
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} else {
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caps = nv_ro32(falcon, 0x12c);
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caps = nvkm_rd32(device, base + 0x12c);
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falcon->version = (caps & 0x0000000f);
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falcon->secret = (caps & 0x00000030) >> 4;
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}
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caps = nv_ro32(falcon, 0x108);
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caps = nvkm_rd32(device, base + 0x108);
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falcon->code.limit = (caps & 0x000001ff) << 8;
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falcon->data.limit = (caps & 0x0003fe00) >> 1;
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@ -105,20 +94,20 @@ _nvkm_falcon_init(struct nvkm_object *object)
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if (falcon->secret && falcon->version < 4) {
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if (!falcon->version) {
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nvkm_msec(device, 2000,
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if (nv_ro32(falcon, 0x008) & 0x00000010)
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if (nvkm_rd32(device, base + 0x008) & 0x00000010)
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break;
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);
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} else {
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nvkm_msec(device, 2000,
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if (!(nv_ro32(falcon, 0x180) & 0x80000000))
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if (!(nvkm_rd32(device, base + 0x180) & 0x80000000))
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break;
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);
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}
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nv_wo32(falcon, 0x004, 0x00000010);
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nvkm_wr32(device, base + 0x004, 0x00000010);
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}
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/* disable all interrupts */
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nv_wo32(falcon, 0x014, 0xffffffff);
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nvkm_wr32(device, base + 0x014, 0xffffffff);
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/* no default ucode provided by the engine implementation, try and
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* locate a "self-bootstrapping" firmware image for the engine
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@ -193,13 +182,13 @@ _nvkm_falcon_init(struct nvkm_object *object)
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/* upload firmware bootloader (or the full code segments) */
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if (falcon->core) {
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if (device->card_type < NV_C0)
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nv_wo32(falcon, 0x618, 0x04000000);
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nvkm_wr32(device, base + 0x618, 0x04000000);
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else
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nv_wo32(falcon, 0x618, 0x00000114);
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nv_wo32(falcon, 0x11c, 0);
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nv_wo32(falcon, 0x110, falcon->core->addr >> 8);
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nv_wo32(falcon, 0x114, 0);
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nv_wo32(falcon, 0x118, 0x00006610);
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nvkm_wr32(device, base + 0x618, 0x00000114);
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nvkm_wr32(device, base + 0x11c, 0);
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nvkm_wr32(device, base + 0x110, falcon->core->addr >> 8);
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nvkm_wr32(device, base + 0x114, 0);
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nvkm_wr32(device, base + 0x118, 0x00006610);
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} else {
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if (falcon->code.size > falcon->code.limit ||
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falcon->data.size > falcon->data.limit) {
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@ -208,39 +197,39 @@ _nvkm_falcon_init(struct nvkm_object *object)
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}
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if (falcon->version < 3) {
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nv_wo32(falcon, 0xff8, 0x00100000);
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nvkm_wr32(device, base + 0xff8, 0x00100000);
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for (i = 0; i < falcon->code.size / 4; i++)
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nv_wo32(falcon, 0xff4, falcon->code.data[i]);
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nvkm_wr32(device, base + 0xff4, falcon->code.data[i]);
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} else {
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nv_wo32(falcon, 0x180, 0x01000000);
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nvkm_wr32(device, base + 0x180, 0x01000000);
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for (i = 0; i < falcon->code.size / 4; i++) {
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if ((i & 0x3f) == 0)
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nv_wo32(falcon, 0x188, i >> 6);
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nv_wo32(falcon, 0x184, falcon->code.data[i]);
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nvkm_wr32(device, base + 0x188, i >> 6);
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nvkm_wr32(device, base + 0x184, falcon->code.data[i]);
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}
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}
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}
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/* upload data segment (if necessary), zeroing the remainder */
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if (falcon->version < 3) {
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nv_wo32(falcon, 0xff8, 0x00000000);
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nvkm_wr32(device, base + 0xff8, 0x00000000);
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for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
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nv_wo32(falcon, 0xff4, falcon->data.data[i]);
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nvkm_wr32(device, base + 0xff4, falcon->data.data[i]);
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for (; i < falcon->data.limit; i += 4)
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nv_wo32(falcon, 0xff4, 0x00000000);
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nvkm_wr32(device, base + 0xff4, 0x00000000);
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} else {
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nv_wo32(falcon, 0x1c0, 0x01000000);
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nvkm_wr32(device, base + 0x1c0, 0x01000000);
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for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
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nv_wo32(falcon, 0x1c4, falcon->data.data[i]);
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nvkm_wr32(device, base + 0x1c4, falcon->data.data[i]);
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for (; i < falcon->data.limit / 4; i++)
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nv_wo32(falcon, 0x1c4, 0x00000000);
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nvkm_wr32(device, base + 0x1c4, 0x00000000);
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}
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/* start it running */
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nv_wo32(falcon, 0x10c, 0x00000001); /* BLOCK_ON_FIFO */
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nv_wo32(falcon, 0x104, 0x00000000); /* ENTRY */
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nv_wo32(falcon, 0x100, 0x00000002); /* TRIGGER */
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nv_wo32(falcon, 0x048, 0x00000003); /* FIFO | CHSW */
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nvkm_wr32(device, base + 0x10c, 0x00000001); /* BLOCK_ON_FIFO */
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nvkm_wr32(device, base + 0x104, 0x00000000); /* ENTRY */
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nvkm_wr32(device, base + 0x100, 0x00000002); /* TRIGGER */
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nvkm_wr32(device, base + 0x048, 0x00000003); /* FIFO | CHSW */
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return 0;
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}
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@ -248,6 +237,8 @@ int
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_nvkm_falcon_fini(struct nvkm_object *object, bool suspend)
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{
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struct nvkm_falcon *falcon = (void *)object;
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struct nvkm_device *device = falcon->engine.subdev.device;
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const u32 base = falcon->addr;
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if (!suspend) {
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nvkm_gpuobj_ref(NULL, &falcon->core);
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@ -258,8 +249,8 @@ _nvkm_falcon_fini(struct nvkm_object *object, bool suspend)
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}
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}
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nv_mo32(falcon, 0x048, 0x00000003, 0x00000000);
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nv_wo32(falcon, 0x014, 0xffffffff);
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nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000);
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nvkm_wr32(device, base + 0x014, 0xffffffff);
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return nvkm_engine_fini(&falcon->engine, suspend);
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}
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@ -100,7 +100,5 @@ g98_mspdec_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = g98_mspdec_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -100,7 +100,5 @@ gf100_mspdec_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = gf100_mspdec_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -100,7 +100,5 @@ gk104_mspdec_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = gk104_mspdec_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -100,7 +100,5 @@ g98_msppp_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = g98_msppp_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -100,7 +100,5 @@ gf100_msppp_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = gf100_msppp_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -101,7 +101,5 @@ g98_msvld_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = g98_msvld_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -100,7 +100,5 @@ gf100_msvld_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = gf100_msvld_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -100,7 +100,5 @@ gk104_msvld_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = gk104_msvld_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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@ -142,7 +142,5 @@ g98_sec_oclass = {
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.dtor = _nvkm_falcon_dtor,
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.init = _nvkm_falcon_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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