drm amdgfx, bochs and one core fix
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commit
6357c8127b
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@ -405,6 +405,7 @@ struct amdgpu_crtc {
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struct amdgpu_flip_work *pflip_works;
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enum amdgpu_flip_status pflip_status;
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int deferred_flip_completion;
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u64 last_flip_vblank;
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/* pll sharing */
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struct amdgpu_atom_ss ss;
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bool ss_enabled;
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@ -303,12 +303,11 @@ static void dm_pflip_high_irq(void *interrupt_params)
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return;
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}
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/* Update to correct count(s) if racing with vblank irq */
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amdgpu_crtc->last_flip_vblank = drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
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/* wake up userspace */
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if (amdgpu_crtc->event) {
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/* Update to correct count(s) if racing with vblank irq */
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drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
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drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
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/* page flip completed. clean up */
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@ -4828,6 +4827,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
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int planes_count = 0;
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unsigned long flags;
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u64 last_flip_vblank;
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bool vrr_active = acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE;
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/* update planes when needed */
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for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
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@ -4859,6 +4860,16 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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/* In commit tail framework this cannot happen */
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WARN_ON(1);
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}
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/* For variable refresh rate mode only:
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* Get vblank of last completed flip to avoid > 1 vrr flips per
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* video frame by use of throttling, but allow flip programming
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* anywhere in the possibly large variable vrr vblank interval
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* for fine-grained flip timing control and more opportunity to
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* avoid stutter on late submission of amdgpu_dm_do_flip() calls.
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*/
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last_flip_vblank = acrtc_attach->last_flip_vblank;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
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@ -4882,10 +4893,18 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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if (plane->type == DRM_PLANE_TYPE_PRIMARY)
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drm_crtc_vblank_get(crtc);
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/* Use old throttling in non-vrr fixed refresh rate mode
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* to keep flip scheduling based on target vblank counts
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* working in a backwards compatible way, e.g., clients
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* using GLX_OML_sync_control extension.
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*/
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if (!vrr_active)
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last_flip_vblank = drm_crtc_vblank_count(crtc);
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amdgpu_dm_do_flip(
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crtc,
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fb,
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(uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
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(uint32_t) last_flip_vblank + *wait_for_vblank,
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dc_state);
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}
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@ -154,6 +154,10 @@ static int bochs_pci_probe(struct pci_dev *pdev,
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if (IS_ERR(dev))
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return PTR_ERR(dev);
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ret = pci_enable_device(pdev);
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if (ret)
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goto err_free_dev;
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dev->pdev = pdev;
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pci_set_drvdata(pdev, dev);
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@ -1602,6 +1602,15 @@ int drm_atomic_helper_async_check(struct drm_device *dev,
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old_plane_state->crtc != new_plane_state->crtc)
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return -EINVAL;
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/*
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* FIXME: Since prepare_fb and cleanup_fb are always called on
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* the new_plane_state for async updates we need to block framebuffer
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* changes. This prevents use of a fb that's been cleaned up and
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* double cleanups from occuring.
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*/
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if (old_plane_state->fb != new_plane_state->fb)
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return -EINVAL;
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funcs = plane->helper_private;
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if (!funcs->atomic_async_update)
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return -EINVAL;
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