mvebu soc changes for v3.14

- orion:
     - remove IRQF_DISABLED
     - directly include some .h files
 
  - mvebu:
     - remove some sparse warnings
 
  - orion5x:
     - include cleanup
     - warning removal for C=1
 
  - kirkwood:
     - remove legacy clock workarounds
     - stop rpinting a TCLK value of 0 for DT boards
 
  - dove:
     - warning removal for C=1
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Merge tag 'mvebu-soc-3.14' of git://git.infradead.org/linux-mvebu into next/cleanup

From Jason Cooper:
mvebu soc changes for v3.14

 - orion:
    - remove IRQF_DISABLED
    - directly include some .h files

 - mvebu:
    - remove some sparse warnings

 - orion5x:
    - include cleanup
    - warning removal for C=1

 - kirkwood:
    - remove legacy clock workarounds
    - stop rpinting a TCLK value of 0 for DT boards

 - dove:
    - warning removal for C=1

* tag 'mvebu-soc-3.14' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: fix some sparse warnings
  ARM: kirkwood: stop printk TCLK value at boot for DT boards
  ARM: orion5x: drop unused include from common.c
  ARM: Dove: Fix compiler warnings with C=1 builds
  ARM: Orion5x: Fix warnings when using C=1.
  ARM: Orion: Add missing includes
  ARM: kirkwood: remove lagacy clk workarounds
  arm: plat-orion: remove deprecated IRQF_DISABLED

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2013-12-03 16:54:28 -08:00
commit 6316756922
20 changed files with 36 additions and 74 deletions

View File

@ -162,7 +162,7 @@ void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
/*****************************************************************************
* SoC RTC
****************************************************************************/
void __init dove_rtc_init(void)
static void __init dove_rtc_init(void)
{
orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}
@ -256,19 +256,10 @@ void __init dove_timer_init(void)
IRQ_DOVE_BRIDGE, dove_tclk);
}
/*****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
void __init dove_crypto_init(void)
{
orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
}
/*****************************************************************************
* XOR 0
****************************************************************************/
void __init dove_xor0_init(void)
static void __init dove_xor0_init(void)
{
orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
@ -277,7 +268,7 @@ void __init dove_xor0_init(void)
/*****************************************************************************
* XOR 1
****************************************************************************/
void __init dove_xor1_init(void)
static void __init dove_xor1_init(void)
{
orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);

View File

@ -10,55 +10,21 @@
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_net.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
#include <linux/dma-mapping.h>
#include <linux/irqchip.h>
#include <linux/kexec.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/bridge-regs.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <plat/irq.h>
#include <plat/common.h>
#include "common.h"
/*
* There are still devices that doesn't know about DT yet. Get clock
* gates here and add a clock lookup alias, so that old platform
* devices still work.
*/
static void __init kirkwood_legacy_clk_init(void)
{
struct device_node *np = of_find_compatible_node(
NULL, NULL, "marvell,kirkwood-gating-clock");
struct of_phandle_args clkspec;
struct clk *clk;
clkspec.np = np;
clkspec.args_count = 1;
/*
* The ethernet interfaces forget the MAC address assigned by
* u-boot if the clocks are turned off. Until proper DT support
* is available we always enable them for now.
*/
clkspec.args[0] = CGC_BIT_GE0;
clk = of_clk_get_from_provider(&clkspec);
clk_prepare_enable(clk);
clkspec.args[0] = CGC_BIT_GE1;
clk = of_clk_get_from_provider(&clkspec);
clk_prepare_enable(clk);
}
#define MV643XX_ETH_MAC_ADDR_LOW 0x0414
#define MV643XX_ETH_MAC_ADDR_HIGH 0x0418
@ -140,7 +106,7 @@ eth_fixup_skip:
static void __init kirkwood_dt_init(void)
{
pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
pr_info("Kirkwood: %s.\n", kirkwood_id());
/*
* Disable propagation of mbus errors to the CPU local bus,
@ -156,8 +122,6 @@ static void __init kirkwood_dt_init(void)
kirkwood_cpufreq_init();
kirkwood_cpuidle_init();
/* Setup clocks for legacy devices */
kirkwood_legacy_clk_init();
kirkwood_pm_init();
kirkwood_dt_eth_fixup();

View File

@ -27,6 +27,7 @@
#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include "armada-370-xp.h"
#include "coherency.h"
unsigned long coherency_phys_base;
static void __iomem *coherency_base;

View File

@ -14,7 +14,9 @@
#ifndef __MACH_370_XP_COHERENCY_H
#define __MACH_370_XP_COHERENCY_H
int set_cpu_coherent(int cpu_id, int smp_group_id);
extern unsigned long coherency_phys_base;
int set_cpu_coherent(unsigned int cpu_id, int smp_group_id);
int coherency_init(void);
#endif /* __MACH_370_XP_COHERENCY_H */

View File

@ -26,7 +26,6 @@ void armada_370_xp_handle_irq(struct pt_regs *regs);
void armada_xp_cpu_die(unsigned int cpu);
int armada_370_xp_coherency_init(void);
int armada_370_xp_pmsu_init(void);
void armada_xp_secondary_startup(void);
extern struct smp_operations armada_xp_smp_ops;
#endif

View File

@ -15,6 +15,7 @@
#include <linux/errno.h>
#include <linux/smp.h>
#include <asm/proc-fns.h>
#include "common.h"
/*
* platform-specific code to shutdown a CPU

View File

@ -46,7 +46,7 @@ static struct clk *__init get_cpu_clk(int cpu)
return cpu_clk;
}
void __init set_secondary_cpus_clock(void)
static void __init set_secondary_cpus_clock(void)
{
int thiscpu, cpu;
unsigned long rate;
@ -94,7 +94,7 @@ static void __init armada_xp_smp_init_cpus(void)
set_smp_cross_call(armada_mpic_send_doorbell);
}
void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *node;
struct resource res;

View File

@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/smp.h>
#include <asm/smp_plat.h>
#include "pmsu.h"
static void __iomem *pmsu_mp_base;
static void __iomem *pmsu_reset_base;
@ -58,7 +59,7 @@ int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr)
}
#endif
int __init armada_370_xp_pmsu_init(void)
static int __init armada_370_xp_pmsu_init(void)
{
struct device_node *np;

View File

@ -27,6 +27,7 @@
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/reboot.h>
#include "common.h"
static void __iomem *system_controller_base;
@ -39,14 +40,14 @@ struct mvebu_system_controller {
};
static struct mvebu_system_controller *mvebu_sc;
const struct mvebu_system_controller armada_370_xp_system_controller = {
static const struct mvebu_system_controller armada_370_xp_system_controller = {
.rstoutn_mask_offset = 0x60,
.system_soft_reset_offset = 0x64,
.rstoutn_mask_reset_out_en = 0x1,
.system_soft_reset = 0x1,
};
const struct mvebu_system_controller orion_system_controller = {
static const struct mvebu_system_controller orion_system_controller = {
.rstoutn_mask_offset = 0x108,
.system_soft_reset_offset = 0x10c,
.rstoutn_mask_reset_out_en = 0x4,

View File

@ -21,7 +21,7 @@
#include <plat/irq.h>
#include "common.h"
struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
NULL),

View File

@ -24,7 +24,6 @@
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/system_misc.h>
#include <asm/timex.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
@ -135,7 +134,7 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
/*****************************************************************************
* SPI
****************************************************************************/
void __init orion5x_spi_init()
void __init orion5x_spi_init(void)
{
orion_spi_init(SPI_PHYS_BASE);
}
@ -185,7 +184,7 @@ static void __init orion5x_crypto_init(void)
/*****************************************************************************
* Watchdog
****************************************************************************/
void __init orion5x_wdt_init(void)
static void __init orion5x_wdt_init(void)
{
orion_wdt_init();
}
@ -246,7 +245,7 @@ void orion5x_setup_wins(void)
int orion5x_tclk;
int __init orion5x_find_tclk(void)
static int __init orion5x_find_tclk(void)
{
u32 dev, rev;

View File

@ -202,7 +202,7 @@ __initcall(db88f5281_7seg_init);
* PCI
****************************************************************************/
void __init db88f5281_pci_preinit(void)
static void __init db88f5281_pci_preinit(void)
{
int pin;

View File

@ -16,6 +16,7 @@
#include <mach/bridge-regs.h>
#include <plat/orion-gpio.h>
#include <plat/irq.h>
#include "common.h"
static int __initdata gpio0_irqs[4] = {
IRQ_ORION5X_GPIO_0_7,

View File

@ -240,11 +240,11 @@ static int __init pcie_setup(struct pci_sys_data *sys)
#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)

View File

@ -108,7 +108,7 @@ static struct platform_device rd88f5182_gpio_leds = {
* PCI
****************************************************************************/
void __init rd88f5182_pci_preinit(void)
static void __init rd88f5182_pci_preinit(void)
{
int pin;

View File

@ -77,7 +77,7 @@ static struct platform_device tsp2_nor_flash = {
#define TSP2_PCI_SLOT0_OFFS 7
#define TSP2_PCI_SLOT0_IRQ_PIN 11
void __init tsp2_pci_preinit(void)
static void __init tsp2_pci_preinit(void)
{
int pin;

View File

@ -106,7 +106,7 @@ static struct platform_device qnap_ts209_nor_flash = {
#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6
#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7
void __init qnap_ts209_pci_preinit(void)
static void __init qnap_ts209_pci_preinit(void)
{
int pin;

View File

@ -57,7 +57,7 @@ static struct map_desc ts78xx_io_desc[] __initdata = {
},
};
void __init ts78xx_map_io(void)
static void __init ts78xx_map_io(void)
{
orion5x_map_io();
iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));

View File

@ -22,6 +22,7 @@
#include <linux/platform_data/dma-mv_xor.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <mach/bridge-regs.h>
#include <plat/common.h>
/* Create a clkdev entry for a given device/clk */
void __init orion_clkdev_add(const char *con_id, const char *dev_id,
@ -256,7 +257,7 @@ static __init void ge_complete(
/*****************************************************************************
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
static struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
static struct resource orion_ge00_shared_resources[] = {
{
@ -322,7 +323,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
/*****************************************************************************
* GE01
****************************************************************************/
struct mv643xx_eth_shared_platform_data orion_ge01_shared_data;
static struct mv643xx_eth_shared_platform_data orion_ge01_shared_data;
static struct resource orion_ge01_shared_resources[] = {
{
@ -373,7 +374,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
/*****************************************************************************
* GE10
****************************************************************************/
struct mv643xx_eth_shared_platform_data orion_ge10_shared_data;
static struct mv643xx_eth_shared_platform_data orion_ge10_shared_data;
static struct resource orion_ge10_shared_resources[] = {
{
@ -422,7 +423,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
/*****************************************************************************
* GE11
****************************************************************************/
struct mv643xx_eth_shared_platform_data orion_ge11_shared_data;
static struct mv643xx_eth_shared_platform_data orion_ge11_shared_data;
static struct resource orion_ge11_shared_resources[] = {
{

View File

@ -17,6 +17,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>
#include <plat/time.h>
/*
* MBus bridge block registers.
@ -174,7 +175,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
static struct irqaction orion_timer_irq = {
.name = "orion_tick",
.flags = IRQF_DISABLED | IRQF_TIMER,
.flags = IRQF_TIMER,
.handler = orion_timer_interrupt
};