qed: Add APIs for flash access.
This patch adds APIs for flash access. Signed-off-by: Sudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com> Signed-off-by: Ariel Elior <ariel.elior@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -81,6 +81,13 @@ enum qed_coalescing_mode {
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QED_COAL_MODE_ENABLE
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};
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enum qed_nvm_cmd {
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QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
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QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
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QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
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QED_GET_MCP_NVM_RESP = 0xFFFFFF00
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};
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struct qed_eth_cb_ops;
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struct qed_dev_info;
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union qed_mcp_protocol_stats;
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@ -12268,8 +12268,11 @@ struct public_drv_mb {
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#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
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#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
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#define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000
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#define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
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#define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
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#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
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#define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
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#define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
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#define DRV_MSG_CODE_MCP_RESET 0x00090000
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#define DRV_MSG_CODE_SET_VERSION 0x000f0000
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#define DRV_MSG_CODE_MCP_HALT 0x00100000
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@ -12323,7 +12326,6 @@ struct public_drv_mb {
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#define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000
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#define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000
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#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
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u32 drv_mb_param;
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@ -12435,7 +12437,10 @@ struct public_drv_mb {
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#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
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#define FW_MSG_CODE_NVM_OK 0x00010000
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#define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
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#define FW_MSG_CODE_PHY_OK 0x00110000
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#define FW_MSG_CODE_OK 0x00160000
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#define FW_MSG_CODE_ERROR 0x00170000
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#define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
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#define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
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@ -569,6 +569,31 @@ int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
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return 0;
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}
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int qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 cmd,
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u32 param,
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u32 *o_mcp_resp,
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u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf)
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{
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struct qed_mcp_mb_params mb_params;
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int rc;
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memset(&mb_params, 0, sizeof(mb_params));
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mb_params.cmd = cmd;
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mb_params.param = param;
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mb_params.p_data_src = i_buf;
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mb_params.data_src_size = (u8)i_txn_size;
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rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
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if (rc)
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return rc;
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*o_mcp_resp = mb_params.mcp_resp;
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*o_mcp_param = mb_params.mcp_param;
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return 0;
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}
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int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 cmd,
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@ -2261,6 +2286,102 @@ int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
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return rc;
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}
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int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt;
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p_ptt = qed_ptt_acquire(p_hwfn);
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if (!p_ptt)
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return -EBUSY;
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memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp));
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qed_ptt_release(p_hwfn, p_ptt);
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return 0;
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}
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int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt;
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u32 resp, param;
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int rc;
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p_ptt = qed_ptt_acquire(p_hwfn);
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if (!p_ptt)
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return -EBUSY;
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rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
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&resp, ¶m);
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cdev->mcp_nvm_resp = resp;
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qed_ptt_release(p_hwfn, p_ptt);
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return rc;
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}
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int qed_mcp_nvm_write(struct qed_dev *cdev,
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u32 cmd, u32 addr, u8 *p_buf, u32 len)
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{
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u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param;
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt;
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int rc = -EINVAL;
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p_ptt = qed_ptt_acquire(p_hwfn);
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if (!p_ptt)
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return -EBUSY;
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switch (cmd) {
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case QED_PUT_FILE_DATA:
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nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
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break;
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case QED_NVM_WRITE_NVRAM:
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nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
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break;
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default:
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DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd);
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rc = -EINVAL;
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goto out;
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}
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while (buf_idx < len) {
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buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN);
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nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
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addr) + buf_idx;
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rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
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&resp, ¶m, buf_size,
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(u32 *)&p_buf[buf_idx]);
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if (rc) {
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DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc);
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resp = FW_MSG_CODE_ERROR;
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break;
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}
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if (resp != FW_MSG_CODE_OK &&
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resp != FW_MSG_CODE_NVM_OK &&
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resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
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DP_NOTICE(cdev,
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"nvm write failed, resp = 0x%08x\n", resp);
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rc = -EINVAL;
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break;
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}
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/* This can be a lengthy process, and it's possible scheduler
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* isn't pre-emptable. Sleep a bit to prevent CPU hogging.
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*/
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if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000)
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usleep_range(1000, 2000);
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buf_idx += buf_size;
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}
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cdev->mcp_nvm_resp = resp;
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out:
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qed_ptt_release(p_hwfn, p_ptt);
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return rc;
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}
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int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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u32 drv_mb_param = 0, rsp, param;
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@ -443,6 +443,40 @@ int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
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*/
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int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len);
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/**
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* @brief Write to nvm
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*
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* @param cdev
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* @param addr - nvm offset
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* @param cmd - nvm command
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* @param p_buf - nvm write buffer
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* @param len - buffer len
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*
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* @return int - 0 - operation was successful.
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*/
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int qed_mcp_nvm_write(struct qed_dev *cdev,
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u32 cmd, u32 addr, u8 *p_buf, u32 len);
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/**
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* @brief Put file begin
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*
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* @param cdev
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* @param addr - nvm offset
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*
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* @return int - 0 - operation was successful.
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*/
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int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr);
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/**
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* @brief Check latest response
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*
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* @param cdev
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* @param p_buf - nvm write buffer
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*
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* @return int - 0 - operation was successful.
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*/
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int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf);
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struct qed_nvm_image_att {
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u32 start_addr;
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u32 length;
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