cpufreq: apple-soc: Add new driver to control Apple SoC CPU P-states
This driver implements CPU frequency scaling for Apple Silicon SoCs, including M1 (t8103), M1 Max/Pro/Ultra (t600x), and M2 (t8112). Each CPU cluster has its own register set, and frequency management is fully automated by the hardware; the driver only has to write one register. There is boost frequency support, but the hardware will only allow their use if only a subset of cores in a cluster are in non-deep-idle. Since we don't support deep idle yet, these frequencies are not achievable, but the driver supports them. They will remain disabled in the device tree until deep idle is implemented, to avoid confusing users. This driver does not yet implement the memory controller performance state tuning that usually accompanies higher CPU p-states. This will be done in a future patch. Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Hector Martin
Viresh Kumar
parent
4370232c72
commit
6286bbb405
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@ -41,6 +41,15 @@ config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
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To compile this driver as a module, choose M here: the
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module will be called sun50i-cpufreq-nvmem.
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config ARM_APPLE_SOC_CPUFREQ
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tristate "Apple Silicon SoC CPUFreq support"
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depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)
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select PM_OPP
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default ARCH_APPLE
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help
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This adds the CPUFreq driver for Apple Silicon machines
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(e.g. Apple M1).
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config ARM_ARMADA_37XX_CPUFREQ
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tristate "Armada 37xx CPUFreq support"
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depends on ARCH_MVEBU && CPUFREQ_DT
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@ -52,6 +52,7 @@ obj-$(CONFIG_X86_AMD_FREQ_SENSITIVITY) += amd_freq_sensitivity.o
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##################################################################################
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# ARM SoC drivers
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obj-$(CONFIG_ARM_APPLE_SOC_CPUFREQ) += apple-soc-cpufreq.o
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obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o
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obj-$(CONFIG_ARM_ARMADA_8K_CPUFREQ) += armada-8k-cpufreq.o
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obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ) += brcmstb-avs-cpufreq.o
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@ -0,0 +1,352 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Apple SoC CPU cluster performance state driver
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*
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* Copyright The Asahi Linux Contributors
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*
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* Based on scpi-cpufreq.c
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/cpumask.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#define APPLE_DVFS_CMD 0x20
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#define APPLE_DVFS_CMD_BUSY BIT(31)
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#define APPLE_DVFS_CMD_SET BIT(25)
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#define APPLE_DVFS_CMD_PS2 GENMASK(16, 12)
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#define APPLE_DVFS_CMD_PS1 GENMASK(4, 0)
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/* Same timebase as CPU counter (24MHz) */
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#define APPLE_DVFS_LAST_CHG_TIME 0x38
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/*
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* Apple ran out of bits and had to shift this in T8112...
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*/
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#define APPLE_DVFS_STATUS 0x50
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#define APPLE_DVFS_STATUS_CUR_PS_T8103 GENMASK(7, 4)
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#define APPLE_DVFS_STATUS_CUR_PS_SHIFT_T8103 4
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#define APPLE_DVFS_STATUS_TGT_PS_T8103 GENMASK(3, 0)
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#define APPLE_DVFS_STATUS_CUR_PS_T8112 GENMASK(9, 5)
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#define APPLE_DVFS_STATUS_CUR_PS_SHIFT_T8112 5
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#define APPLE_DVFS_STATUS_TGT_PS_T8112 GENMASK(4, 0)
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/*
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* Div is +1, base clock is 12MHz on existing SoCs.
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* For documentation purposes. We use the OPP table to
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* get the frequency.
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*/
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#define APPLE_DVFS_PLL_STATUS 0xc0
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#define APPLE_DVFS_PLL_FACTOR 0xc8
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#define APPLE_DVFS_PLL_FACTOR_MULT GENMASK(31, 16)
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#define APPLE_DVFS_PLL_FACTOR_DIV GENMASK(15, 0)
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#define APPLE_DVFS_TRANSITION_TIMEOUT 100
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struct apple_soc_cpufreq_info {
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u64 max_pstate;
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u64 cur_pstate_mask;
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u64 cur_pstate_shift;
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};
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struct apple_cpu_priv {
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struct device *cpu_dev;
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void __iomem *reg_base;
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const struct apple_soc_cpufreq_info *info;
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};
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static struct cpufreq_driver apple_soc_cpufreq_driver;
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static const struct apple_soc_cpufreq_info soc_t8103_info = {
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.max_pstate = 15,
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.cur_pstate_mask = APPLE_DVFS_STATUS_CUR_PS_T8103,
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.cur_pstate_shift = APPLE_DVFS_STATUS_CUR_PS_SHIFT_T8103,
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};
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static const struct apple_soc_cpufreq_info soc_t8112_info = {
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.max_pstate = 31,
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.cur_pstate_mask = APPLE_DVFS_STATUS_CUR_PS_T8112,
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.cur_pstate_shift = APPLE_DVFS_STATUS_CUR_PS_SHIFT_T8112,
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};
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static const struct apple_soc_cpufreq_info soc_default_info = {
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.max_pstate = 15,
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.cur_pstate_mask = 0, /* fallback */
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};
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static const struct of_device_id apple_soc_cpufreq_of_match[] = {
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{
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.compatible = "apple,t8103-cluster-cpufreq",
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.data = &soc_t8103_info,
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},
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{
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.compatible = "apple,t8112-cluster-cpufreq",
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.data = &soc_t8112_info,
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},
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{
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.compatible = "apple,cluster-cpufreq",
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.data = &soc_default_info,
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},
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{}
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};
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static unsigned int apple_soc_cpufreq_get_rate(unsigned int cpu)
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{
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struct cpufreq_policy *policy = cpufreq_cpu_get_raw(cpu);
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struct apple_cpu_priv *priv = policy->driver_data;
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struct cpufreq_frequency_table *p;
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unsigned int pstate;
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if (priv->info->cur_pstate_mask) {
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u64 reg = readq_relaxed(priv->reg_base + APPLE_DVFS_STATUS);
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pstate = (reg & priv->info->cur_pstate_mask) >> priv->info->cur_pstate_shift;
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} else {
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/*
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* For the fallback case we might not know the layout of DVFS_STATUS,
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* so just use the command register value (which ignores boost limitations).
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*/
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u64 reg = readq_relaxed(priv->reg_base + APPLE_DVFS_CMD);
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pstate = FIELD_GET(APPLE_DVFS_CMD_PS1, reg);
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}
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cpufreq_for_each_valid_entry(p, policy->freq_table)
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if (p->driver_data == pstate)
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return p->frequency;
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dev_err(priv->cpu_dev, "could not find frequency for pstate %d\n",
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pstate);
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return 0;
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}
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static int apple_soc_cpufreq_set_target(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct apple_cpu_priv *priv = policy->driver_data;
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unsigned int pstate = policy->freq_table[index].driver_data;
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u64 reg;
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/* Fallback for newer SoCs */
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if (index > priv->info->max_pstate)
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index = priv->info->max_pstate;
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if (readq_poll_timeout_atomic(priv->reg_base + APPLE_DVFS_CMD, reg,
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!(reg & APPLE_DVFS_CMD_BUSY), 2,
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APPLE_DVFS_TRANSITION_TIMEOUT)) {
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return -EIO;
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}
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reg &= ~(APPLE_DVFS_CMD_PS1 | APPLE_DVFS_CMD_PS2);
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reg |= FIELD_PREP(APPLE_DVFS_CMD_PS1, pstate);
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reg |= FIELD_PREP(APPLE_DVFS_CMD_PS2, pstate);
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reg |= APPLE_DVFS_CMD_SET;
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writeq_relaxed(reg, priv->reg_base + APPLE_DVFS_CMD);
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return 0;
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}
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static unsigned int apple_soc_cpufreq_fast_switch(struct cpufreq_policy *policy,
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unsigned int target_freq)
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{
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if (apple_soc_cpufreq_set_target(policy, policy->cached_resolved_idx) < 0)
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return 0;
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return policy->freq_table[policy->cached_resolved_idx].frequency;
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}
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static int apple_soc_cpufreq_find_cluster(struct cpufreq_policy *policy,
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void __iomem **reg_base,
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const struct apple_soc_cpufreq_info **info)
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{
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struct of_phandle_args args;
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const struct of_device_id *match;
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int ret = 0;
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ret = of_perf_domain_get_sharing_cpumask(policy->cpu, "performance-domains",
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"#performance-domain-cells",
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policy->cpus, &args);
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if (ret < 0)
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return ret;
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match = of_match_node(apple_soc_cpufreq_of_match, args.np);
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of_node_put(args.np);
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if (!match)
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return -ENODEV;
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*info = match->data;
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*reg_base = of_iomap(args.np, 0);
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if (IS_ERR(*reg_base))
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return PTR_ERR(*reg_base);
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return 0;
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}
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static struct freq_attr *apple_soc_cpufreq_hw_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL, /* Filled in below if boost is enabled */
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NULL,
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};
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static int apple_soc_cpufreq_init(struct cpufreq_policy *policy)
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{
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int ret, i;
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unsigned int transition_latency;
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void __iomem *reg_base;
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struct device *cpu_dev;
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struct apple_cpu_priv *priv;
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const struct apple_soc_cpufreq_info *info;
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struct cpufreq_frequency_table *freq_table;
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cpu_dev = get_cpu_device(policy->cpu);
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if (!cpu_dev) {
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pr_err("failed to get cpu%d device\n", policy->cpu);
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return -ENODEV;
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}
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ret = dev_pm_opp_of_add_table(cpu_dev);
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if (ret < 0) {
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dev_err(cpu_dev, "%s: failed to add OPP table: %d\n", __func__, ret);
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return ret;
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}
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ret = apple_soc_cpufreq_find_cluster(policy, ®_base, &info);
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if (ret) {
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dev_err(cpu_dev, "%s: failed to get cluster info: %d\n", __func__, ret);
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return ret;
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}
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ret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
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if (ret) {
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dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n", __func__, ret);
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goto out_iounmap;
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}
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ret = dev_pm_opp_get_opp_count(cpu_dev);
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if (ret <= 0) {
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dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n");
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ret = -EPROBE_DEFER;
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goto out_free_opp;
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}
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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ret = -ENOMEM;
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goto out_free_opp;
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}
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ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
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if (ret) {
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dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
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goto out_free_priv;
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}
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/* Get OPP levels (p-state indexes) and stash them in driver_data */
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for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
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unsigned long rate = freq_table[i].frequency * 1000 + 999;
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struct dev_pm_opp *opp = dev_pm_opp_find_freq_floor(cpu_dev, &rate);
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if (IS_ERR(opp)) {
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ret = PTR_ERR(opp);
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goto out_free_cpufreq_table;
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}
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freq_table[i].driver_data = dev_pm_opp_get_level(opp);
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dev_pm_opp_put(opp);
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}
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priv->cpu_dev = cpu_dev;
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priv->reg_base = reg_base;
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priv->info = info;
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policy->driver_data = priv;
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policy->freq_table = freq_table;
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transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev);
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if (!transition_latency)
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transition_latency = CPUFREQ_ETERNAL;
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policy->cpuinfo.transition_latency = transition_latency;
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policy->dvfs_possible_from_any_cpu = true;
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policy->fast_switch_possible = true;
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if (policy_has_boost_freq(policy)) {
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ret = cpufreq_enable_boost_support();
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if (ret) {
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dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
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} else {
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apple_soc_cpufreq_hw_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
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apple_soc_cpufreq_driver.boost_enabled = true;
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}
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}
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return 0;
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out_free_cpufreq_table:
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dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
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out_free_priv:
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kfree(priv);
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out_free_opp:
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dev_pm_opp_remove_all_dynamic(cpu_dev);
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out_iounmap:
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iounmap(reg_base);
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return ret;
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}
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static int apple_soc_cpufreq_exit(struct cpufreq_policy *policy)
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{
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struct apple_cpu_priv *priv = policy->driver_data;
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dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
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dev_pm_opp_remove_all_dynamic(priv->cpu_dev);
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iounmap(priv->reg_base);
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kfree(priv);
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return 0;
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}
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static struct cpufreq_driver apple_soc_cpufreq_driver = {
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.name = "apple-cpufreq",
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.flags = CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
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CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_IS_COOLING_DEV,
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.verify = cpufreq_generic_frequency_table_verify,
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.attr = cpufreq_generic_attr,
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.get = apple_soc_cpufreq_get_rate,
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.init = apple_soc_cpufreq_init,
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.exit = apple_soc_cpufreq_exit,
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.target_index = apple_soc_cpufreq_set_target,
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.fast_switch = apple_soc_cpufreq_fast_switch,
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.register_em = cpufreq_register_em_with_opp,
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.attr = apple_soc_cpufreq_hw_attr,
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};
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static int __init apple_soc_cpufreq_module_init(void)
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{
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if (!of_machine_is_compatible("apple,arm-platform"))
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return -ENODEV;
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return cpufreq_register_driver(&apple_soc_cpufreq_driver);
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}
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module_init(apple_soc_cpufreq_module_init);
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static void __exit apple_soc_cpufreq_module_exit(void)
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{
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cpufreq_unregister_driver(&apple_soc_cpufreq_driver);
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}
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module_exit(apple_soc_cpufreq_module_exit);
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MODULE_DEVICE_TABLE(of, apple_soc_cpufreq_of_match);
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MODULE_AUTHOR("Hector Martin <marcan@marcan.st>");
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MODULE_DESCRIPTION("Apple SoC CPU cluster DVFS driver");
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MODULE_LICENSE("GPL");
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@ -103,6 +103,8 @@ static const struct of_device_id allowlist[] __initconst = {
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static const struct of_device_id blocklist[] __initconst = {
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{ .compatible = "allwinner,sun50i-h6", },
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{ .compatible = "apple,arm-platform", },
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{ .compatible = "arm,vexpress", },
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{ .compatible = "calxeda,highbank", },
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