staging: comedi: ni_mio_common: remove forward declaration 23
Move ni_set_master_clock() and its helper functions to remove the need for the forward declaration. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
ae43763d34
commit
624b161f7e
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@ -201,9 +201,6 @@ static int ni_ao_fifo_half_empty(struct comedi_device *dev,
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#endif
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static void ni_handle_fifo_dregs(struct comedi_device *dev);
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static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
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unsigned period_ns);
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enum aimodes {
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AIMODE_NONE = 0,
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AIMODE_HALF_FULL = 1,
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@ -4687,6 +4684,203 @@ static int init_cs5529(struct comedi_device *dev)
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return 0;
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}
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/*
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* Find best multiplier/divider to try and get the PLL running at 80 MHz
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* given an arbitrary frequency input clock.
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*/
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static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
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unsigned *freq_divider,
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unsigned *freq_multiplier,
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unsigned *actual_period_ns)
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{
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unsigned div;
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unsigned best_div = 1;
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static const unsigned max_div = 0x10;
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unsigned mult;
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unsigned best_mult = 1;
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static const unsigned max_mult = 0x100;
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static const unsigned pico_per_nano = 1000;
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const unsigned reference_picosec = reference_period_ns * pico_per_nano;
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/* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
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* 20 MHz for most timing clocks */
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static const unsigned target_picosec = 12500;
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static const unsigned fudge_factor_80_to_20Mhz = 4;
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int best_period_picosec = 0;
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for (div = 1; div <= max_div; ++div) {
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for (mult = 1; mult <= max_mult; ++mult) {
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unsigned new_period_ps =
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(reference_picosec * div) / mult;
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if (abs(new_period_ps - target_picosec) <
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abs(best_period_picosec - target_picosec)) {
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best_period_picosec = new_period_ps;
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best_div = div;
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best_mult = mult;
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}
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}
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}
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if (best_period_picosec == 0) {
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printk("%s: bug, failed to find pll parameters\n", __func__);
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return -EIO;
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}
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*freq_divider = best_div;
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*freq_multiplier = best_mult;
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*actual_period_ns =
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(best_period_picosec * fudge_factor_80_to_20Mhz +
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(pico_per_nano / 2)) / pico_per_nano;
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return 0;
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}
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static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
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unsigned source, unsigned period_ns)
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{
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struct ni_private *devpriv = dev->private;
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static const unsigned min_period_ns = 50;
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static const unsigned max_period_ns = 1000;
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static const unsigned timeout = 1000;
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unsigned pll_control_bits;
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unsigned freq_divider;
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unsigned freq_multiplier;
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unsigned i;
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int retval;
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if (source == NI_MIO_PLL_PXI10_CLOCK)
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period_ns = 100;
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/* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
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if (period_ns < min_period_ns || period_ns > max_period_ns) {
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printk
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("%s: you must specify an input clock frequency between %i and %i nanosec "
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"for the phased-lock loop.\n", __func__,
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min_period_ns, max_period_ns);
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return -EINVAL;
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}
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devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
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devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
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RTSI_Trig_Direction_Register);
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pll_control_bits =
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MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
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devpriv->clock_and_fout2 |=
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MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
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devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
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switch (source) {
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case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
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devpriv->clock_and_fout2 |=
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MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
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retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
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&freq_multiplier,
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&devpriv->clock_ns);
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if (retval < 0)
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return retval;
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break;
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case NI_MIO_PLL_PXI10_CLOCK:
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/* pxi clock is 10MHz */
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devpriv->clock_and_fout2 |=
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MSeries_PLL_In_Source_Select_PXI_Clock10;
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retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
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&freq_multiplier,
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&devpriv->clock_ns);
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if (retval < 0)
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return retval;
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break;
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default:
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{
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unsigned rtsi_channel;
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static const unsigned max_rtsi_channel = 7;
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for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
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++rtsi_channel) {
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if (source ==
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NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
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devpriv->clock_and_fout2 |=
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MSeries_PLL_In_Source_Select_RTSI_Bits
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(rtsi_channel);
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break;
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}
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}
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if (rtsi_channel > max_rtsi_channel)
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return -EINVAL;
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retval = ni_mseries_get_pll_parameters(period_ns,
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&freq_divider,
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&freq_multiplier,
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&devpriv->
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clock_ns);
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if (retval < 0)
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return retval;
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}
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break;
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}
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ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
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pll_control_bits |=
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MSeries_PLL_Divisor_Bits(freq_divider) |
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MSeries_PLL_Multiplier_Bits(freq_multiplier);
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/* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
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* freq_divider, freq_multiplier, pll_control_bits); */
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/* printk("clock_ns=%d\n", devpriv->clock_ns); */
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ni_writew(pll_control_bits, M_Offset_PLL_Control);
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devpriv->clock_source = source;
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/* it seems to typically take a few hundred microseconds for PLL to lock */
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for (i = 0; i < timeout; ++i) {
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if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
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break;
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udelay(1);
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}
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if (i == timeout) {
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printk
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("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
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__func__, source, period_ns);
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return -ETIMEDOUT;
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}
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return 3;
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}
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static int ni_set_master_clock(struct comedi_device *dev,
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unsigned source, unsigned period_ns)
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{
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const struct ni_board_struct *board = comedi_board(dev);
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struct ni_private *devpriv = dev->private;
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if (source == NI_MIO_INTERNAL_CLOCK) {
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devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
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devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
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RTSI_Trig_Direction_Register);
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devpriv->clock_ns = TIMEBASE_1_NS;
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if (board->reg_type & ni_reg_m_series_mask) {
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devpriv->clock_and_fout2 &=
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~(MSeries_Timebase1_Select_Bit |
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MSeries_Timebase3_Select_Bit);
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ni_writew(devpriv->clock_and_fout2,
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M_Offset_Clock_and_Fout2);
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ni_writew(0, M_Offset_PLL_Control);
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}
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devpriv->clock_source = source;
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} else {
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if (board->reg_type & ni_reg_m_series_mask) {
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return ni_mseries_set_pll_master_clock(dev, source,
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period_ns);
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} else {
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if (source == NI_MIO_RTSI_CLOCK) {
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devpriv->rtsi_trig_direction_reg |=
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Use_RTSI_Clock_Bit;
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devpriv->stc_writew(dev,
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devpriv->
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rtsi_trig_direction_reg,
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RTSI_Trig_Direction_Register);
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if (period_ns == 0) {
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printk
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("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
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__func__);
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return -EINVAL;
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} else {
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devpriv->clock_ns = period_ns;
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}
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devpriv->clock_source = source;
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} else
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return -EINVAL;
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}
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}
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return 3;
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}
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static unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
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{
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const struct ni_board_struct *board = comedi_board(dev);
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@ -5410,198 +5604,3 @@ static void GPCT_Reset(struct comedi_device *dev, int chan)
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}
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#endif
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/* Find best multiplier/divider to try and get the PLL running at 80 MHz
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* given an arbitrary frequency input clock */
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static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
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unsigned *freq_divider,
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unsigned *freq_multiplier,
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unsigned *actual_period_ns)
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{
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unsigned div;
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unsigned best_div = 1;
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static const unsigned max_div = 0x10;
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unsigned mult;
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unsigned best_mult = 1;
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static const unsigned max_mult = 0x100;
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static const unsigned pico_per_nano = 1000;
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const unsigned reference_picosec = reference_period_ns * pico_per_nano;
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/* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
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* 20 MHz for most timing clocks */
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static const unsigned target_picosec = 12500;
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static const unsigned fudge_factor_80_to_20Mhz = 4;
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int best_period_picosec = 0;
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for (div = 1; div <= max_div; ++div) {
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for (mult = 1; mult <= max_mult; ++mult) {
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unsigned new_period_ps =
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(reference_picosec * div) / mult;
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if (abs(new_period_ps - target_picosec) <
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abs(best_period_picosec - target_picosec)) {
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best_period_picosec = new_period_ps;
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best_div = div;
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best_mult = mult;
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}
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}
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}
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if (best_period_picosec == 0) {
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printk("%s: bug, failed to find pll parameters\n", __func__);
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return -EIO;
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}
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*freq_divider = best_div;
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*freq_multiplier = best_mult;
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*actual_period_ns =
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(best_period_picosec * fudge_factor_80_to_20Mhz +
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(pico_per_nano / 2)) / pico_per_nano;
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return 0;
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}
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static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
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unsigned source, unsigned period_ns)
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{
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struct ni_private *devpriv = dev->private;
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static const unsigned min_period_ns = 50;
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static const unsigned max_period_ns = 1000;
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static const unsigned timeout = 1000;
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unsigned pll_control_bits;
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unsigned freq_divider;
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unsigned freq_multiplier;
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unsigned i;
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int retval;
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if (source == NI_MIO_PLL_PXI10_CLOCK)
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period_ns = 100;
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/* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
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if (period_ns < min_period_ns || period_ns > max_period_ns) {
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printk
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("%s: you must specify an input clock frequency between %i and %i nanosec "
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"for the phased-lock loop.\n", __func__,
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min_period_ns, max_period_ns);
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return -EINVAL;
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}
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devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
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devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
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RTSI_Trig_Direction_Register);
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pll_control_bits =
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MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
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devpriv->clock_and_fout2 |=
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MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
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devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
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switch (source) {
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case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
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devpriv->clock_and_fout2 |=
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MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
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retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
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&freq_multiplier,
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&devpriv->clock_ns);
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if (retval < 0)
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return retval;
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break;
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case NI_MIO_PLL_PXI10_CLOCK:
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/* pxi clock is 10MHz */
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devpriv->clock_and_fout2 |=
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MSeries_PLL_In_Source_Select_PXI_Clock10;
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retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
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&freq_multiplier,
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&devpriv->clock_ns);
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if (retval < 0)
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return retval;
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break;
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default:
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{
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unsigned rtsi_channel;
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static const unsigned max_rtsi_channel = 7;
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for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
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++rtsi_channel) {
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if (source ==
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NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
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devpriv->clock_and_fout2 |=
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MSeries_PLL_In_Source_Select_RTSI_Bits
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(rtsi_channel);
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break;
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}
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}
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if (rtsi_channel > max_rtsi_channel)
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return -EINVAL;
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retval = ni_mseries_get_pll_parameters(period_ns,
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&freq_divider,
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&freq_multiplier,
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&devpriv->
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clock_ns);
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if (retval < 0)
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return retval;
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}
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break;
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}
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ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
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pll_control_bits |=
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MSeries_PLL_Divisor_Bits(freq_divider) |
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MSeries_PLL_Multiplier_Bits(freq_multiplier);
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/* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
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* freq_divider, freq_multiplier, pll_control_bits); */
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/* printk("clock_ns=%d\n", devpriv->clock_ns); */
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ni_writew(pll_control_bits, M_Offset_PLL_Control);
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devpriv->clock_source = source;
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/* it seems to typically take a few hundred microseconds for PLL to lock */
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for (i = 0; i < timeout; ++i) {
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if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
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break;
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udelay(1);
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}
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if (i == timeout) {
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printk
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("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
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__func__, source, period_ns);
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return -ETIMEDOUT;
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}
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return 3;
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}
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static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
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unsigned period_ns)
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{
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const struct ni_board_struct *board = comedi_board(dev);
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struct ni_private *devpriv = dev->private;
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if (source == NI_MIO_INTERNAL_CLOCK) {
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devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
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devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
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RTSI_Trig_Direction_Register);
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devpriv->clock_ns = TIMEBASE_1_NS;
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if (board->reg_type & ni_reg_m_series_mask) {
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devpriv->clock_and_fout2 &=
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~(MSeries_Timebase1_Select_Bit |
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MSeries_Timebase3_Select_Bit);
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ni_writew(devpriv->clock_and_fout2,
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M_Offset_Clock_and_Fout2);
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ni_writew(0, M_Offset_PLL_Control);
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}
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devpriv->clock_source = source;
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} else {
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if (board->reg_type & ni_reg_m_series_mask) {
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return ni_mseries_set_pll_master_clock(dev, source,
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period_ns);
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} else {
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if (source == NI_MIO_RTSI_CLOCK) {
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devpriv->rtsi_trig_direction_reg |=
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Use_RTSI_Clock_Bit;
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devpriv->stc_writew(dev,
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devpriv->
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rtsi_trig_direction_reg,
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RTSI_Trig_Direction_Register);
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if (period_ns == 0) {
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printk
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("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
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__func__);
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return -EINVAL;
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} else {
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devpriv->clock_ns = period_ns;
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}
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devpriv->clock_source = source;
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} else
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return -EINVAL;
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}
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}
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return 3;
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}
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