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drm/amd/display: remove hw_crtc_timing 

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tony Cheng 2017-01-14 18:57:57 -05:00 committed by Alex Deucher
parent ac0e562c52
commit 6235b23cb9
4 changed files with 3 additions and 43 deletions
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2
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
View File

@ -681,7 +681,7 @@ static void dce110_stream_encoder_dp_unblank(
uint64_t m_vid_l = n_vid;
m_vid_l *= param->crtc_timing.pixel_clock;
m_vid_l *= param->pixel_clk_khz;
m_vid_l = div_u64(m_vid_l,
param->link_settings.link_rate
* LINK_RATE_REF_FREQ_IN_KHZ);

2
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -886,7 +886,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
struct encoder_unblank_param params = { { 0 } };
/* only 3 items below are used by unblank */
params.crtc_timing.pixel_clock =
params.pixel_clk_khz =
pipe_ctx->stream->public.timing.pix_clk_khz;
params.link_settings.link_rate = link_settings->link_rate;
pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, &params);

2
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
View File

@ -36,8 +36,8 @@ struct encoder_info_frame {
};
struct encoder_unblank_param {
struct hw_crtc_timing crtc_timing;
struct dc_link_settings link_settings;
unsigned int pixel_clk_khz;
};
struct encoder_set_dp_phy_pattern_param {

40
drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
View File

@ -40,46 +40,6 @@ struct drr_params {
uint32_t vertical_total_max;
};
/* CRTC timing structure */
struct hw_crtc_timing {
uint32_t h_total;
uint32_t h_addressable;
uint32_t h_overscan_left;
uint32_t h_overscan_right;
uint32_t h_sync_start;
uint32_t h_sync_width;
uint32_t v_total;
uint32_t v_addressable;
uint32_t v_overscan_top;
uint32_t v_overscan_bottom;
uint32_t v_sync_start;
uint32_t v_sync_width;
/* in KHz */
uint32_t pixel_clock;
struct {
uint32_t INTERLACED:1;
uint32_t DOUBLESCAN:1;
uint32_t PIXEL_REPETITION:4; /* 1...10 */
uint32_t HSYNC_POSITIVE_POLARITY:1;
uint32_t VSYNC_POSITIVE_POLARITY:1;
/* frame should be packed for 3D
* (currently this refers to HDMI 1.4a FramePacking format */
uint32_t HORZ_COUNT_BY_TWO:1;
uint32_t PACK_3D_FRAME:1;
/* 0 - left eye polarity, 1 - right eye polarity */
uint32_t RIGHT_EYE_3D_POLARITY:1;
/* DVI-DL High-Color mode */
uint32_t HIGH_COLOR_DL_MODE:1;
uint32_t Y_ONLY:1;
/* HDMI 2.0 - Support scrambling for TMDS character
* rates less than or equal to 340Mcsc */
uint32_t LTE_340MCSC_SCRAMBLE:1;
} flags;
};
/* TODO hw_info_frame and hw_info_packet structures are same as in encoder
* merge it*/
struct hw_info_packet {