drm/amd/display: Request usb4 bw for mst streams
[ Upstream commit 5f3bce13266e6fe2f7a46f94d8bc94d5274e276b ]
[WHY]
When usb4 bandwidth allocation mode is enabled, driver need to request
bandwidth from connection manager. For mst link, the requested
bandwidth should be big enough for all remote streams.
[HOW]
- If mst link, the requested bandwidth should be the sum of all mst
streams bandwidth added with dp MTPH overhead.
- Allocate/deallcate usb4 bandwidth when setting dpms on/off.
- When doing display mode validation, driver also need to consider total
bandwidth of all mst streams for mst link.
Reviewed-by: Cruise Hung <cruise.hung@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Peichen Huang <peichen.huang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: 0484e05d048b ("drm/amd/display: fixed integer types and null check locations")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Peichen Huang
Greg Kroah-Hartman
parent
c3682b63c6
commit
622c827544
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@ -1110,23 +1110,25 @@ struct dc_panel_config {
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} ilr;
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};
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#define MAX_SINKS_PER_LINK 4
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/*
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* USB4 DPIA BW ALLOCATION STRUCTS
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*/
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struct dc_dpia_bw_alloc {
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int sink_verified_bw; // The Verified BW that sink can allocated and use that has been verified already
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int sink_allocated_bw; // The Actual Allocated BW that sink currently allocated
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int sink_max_bw; // The Max BW that sink can require/support
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int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks
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int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already
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int link_max_bw; // The Max BW that link can require/support
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int allocated_bw; // The Actual Allocated BW for this DPIA
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int estimated_bw; // The estimated available BW for this DPIA
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int bw_granularity; // BW Granularity
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int dp_overhead; // DP overhead in dp tunneling
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bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM
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bool response_ready; // Response ready from the CM side
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uint8_t nrd_max_lane_count; // Non-reduced max lane count
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uint8_t nrd_max_link_rate; // Non-reduced max link rate
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};
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#define MAX_SINKS_PER_LINK 4
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enum dc_hpd_enable_select {
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HPD_EN_FOR_ALL_EDP = 0,
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HPD_EN_FOR_PRIMARY_EDP_ONLY,
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@ -2071,17 +2071,11 @@ static enum dc_status enable_link_dp(struct dc_state *state,
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}
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}
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/*
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* If the link is DP-over-USB4 do the following:
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* - Train with fallback when enabling DPIA link. Conventional links are
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/* Train with fallback when enabling DPIA link. Conventional links are
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* trained with fallback during sink detection.
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* - Allocate only what the stream needs for bw in Gbps. Inform the CM
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* in case stream needs more or less bw from what has been allocated
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* earlier at plug time.
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*/
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if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
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if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
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do_fallback = true;
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}
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/*
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* Temporary w/a to get DP2.0 link rates to work with SST.
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@ -2263,6 +2257,32 @@ static enum dc_status enable_link(
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return status;
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}
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static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw)
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{
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return true;
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}
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static bool allocate_usb4_bandwidth(struct dc_stream_state *stream)
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{
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bool ret;
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int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing,
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dc_link_get_highest_encoding_format(stream->sink->link));
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ret = allocate_usb4_bandwidth_for_stream(stream, bw);
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return ret;
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}
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static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream)
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{
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bool ret;
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ret = allocate_usb4_bandwidth_for_stream(stream, 0);
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return ret;
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}
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void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
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{
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struct dc *dc = pipe_ctx->stream->ctx->dc;
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@ -2299,6 +2319,9 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
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update_psp_stream_config(pipe_ctx, true);
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dc->hwss.blank_stream(pipe_ctx);
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if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
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deallocate_usb4_bandwidth(pipe_ctx->stream);
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
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deallocate_mst_payload(pipe_ctx);
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else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
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@ -2520,6 +2543,9 @@ void link_set_dpms_on(
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}
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}
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if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
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allocate_usb4_bandwidth(pipe_ctx->stream);
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
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allocate_mst_payload(pipe_ctx);
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else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
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@ -346,23 +346,61 @@ enum dc_status link_validate_mode_timing(
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return DC_OK;
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}
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/*
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* This function calculates the bandwidth required for the stream timing
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* and aggregates the stream bandwidth for the respective dpia link
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*
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* @stream: pointer to the dc_stream_state struct instance
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* @num_streams: number of streams to be validated
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*
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* return: true if validation is succeeded
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*/
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bool link_validate_dpia_bandwidth(const struct dc_stream_state *stream, const unsigned int num_streams)
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{
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bool ret = true;
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int bw_needed[MAX_DPIA_NUM];
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struct dc_link *link[MAX_DPIA_NUM];
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if (!num_streams || num_streams > MAX_DPIA_NUM)
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return ret;
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int bw_needed[MAX_DPIA_NUM] = {0};
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struct dc_link *dpia_link[MAX_DPIA_NUM] = {0};
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int num_dpias = 0;
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for (uint8_t i = 0; i < num_streams; ++i) {
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if (stream[i].signal == SIGNAL_TYPE_DISPLAY_PORT) {
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/* new dpia sst stream, check whether it exceeds max dpia */
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if (num_dpias >= MAX_DPIA_NUM)
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return false;
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link[i] = stream[i].link;
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bw_needed[i] = dc_bandwidth_in_kbps_from_timing(&stream[i].timing,
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dc_link_get_highest_encoding_format(link[i]));
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dpia_link[num_dpias] = stream[i].link;
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bw_needed[num_dpias] = dc_bandwidth_in_kbps_from_timing(&stream[i].timing,
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dc_link_get_highest_encoding_format(dpia_link[num_dpias]));
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num_dpias++;
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} else if (stream[i].signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
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uint8_t j = 0;
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/* check whether its a known dpia link */
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for (; j < num_dpias; ++j) {
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if (dpia_link[j] == stream[i].link)
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break;
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}
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if (j == num_dpias) {
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/* new dpia mst stream, check whether it exceeds max dpia */
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if (num_dpias >= MAX_DPIA_NUM)
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return false;
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else {
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dpia_link[j] = stream[i].link;
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num_dpias++;
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}
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}
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bw_needed[j] += dc_bandwidth_in_kbps_from_timing(&stream[i].timing,
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dc_link_get_highest_encoding_format(dpia_link[j]));
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}
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}
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ret = dpia_validate_usb4_bw(link, bw_needed, num_streams);
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/* Include dp overheads */
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for (uint8_t i = 0; i < num_dpias; ++i) {
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int dp_overhead = 0;
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return ret;
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dp_overhead = link_dp_dpia_get_dp_overhead_in_dp_tunneling(dpia_link[i]);
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bw_needed[i] += dp_overhead;
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}
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return dpia_validate_usb4_bw(dpia_link, bw_needed, num_dpias);
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}
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@ -54,12 +54,18 @@ static bool get_bw_alloc_proceed_flag(struct dc_link *tmp)
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static void reset_bw_alloc_struct(struct dc_link *link)
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{
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link->dpia_bw_alloc_config.bw_alloc_enabled = false;
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link->dpia_bw_alloc_config.sink_verified_bw = 0;
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link->dpia_bw_alloc_config.sink_max_bw = 0;
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link->dpia_bw_alloc_config.link_verified_bw = 0;
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link->dpia_bw_alloc_config.link_max_bw = 0;
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link->dpia_bw_alloc_config.allocated_bw = 0;
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link->dpia_bw_alloc_config.estimated_bw = 0;
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link->dpia_bw_alloc_config.bw_granularity = 0;
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link->dpia_bw_alloc_config.dp_overhead = 0;
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link->dpia_bw_alloc_config.response_ready = false;
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link->dpia_bw_alloc_config.sink_allocated_bw = 0;
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link->dpia_bw_alloc_config.nrd_max_lane_count = 0;
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link->dpia_bw_alloc_config.nrd_max_link_rate = 0;
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for (int i = 0; i < MAX_SINKS_PER_LINK; i++)
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link->dpia_bw_alloc_config.remote_sink_req_bw[i] = 0;
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DC_LOG_DEBUG("reset usb4 bw alloc of link(%d)\n", link->link_index);
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}
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#define BW_GRANULARITY_0 4 // 0.25 Gbps
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@ -210,8 +216,8 @@ static int get_host_router_total_dp_tunnel_bw(const struct dc *dc, uint8_t hr_in
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link_dpia_primary->dpia_bw_alloc_config.bw_alloc_enabled) &&
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(link_dpia_secondary->hpd_status &&
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link_dpia_secondary->dpia_bw_alloc_config.bw_alloc_enabled)) {
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total_bw += link_dpia_primary->dpia_bw_alloc_config.estimated_bw +
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link_dpia_secondary->dpia_bw_alloc_config.sink_allocated_bw;
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total_bw += link_dpia_primary->dpia_bw_alloc_config.estimated_bw +
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link_dpia_secondary->dpia_bw_alloc_config.allocated_bw;
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} else if (link_dpia_primary->hpd_status &&
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link_dpia_primary->dpia_bw_alloc_config.bw_alloc_enabled) {
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total_bw = link_dpia_primary->dpia_bw_alloc_config.estimated_bw;
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@ -264,7 +270,7 @@ static void set_usb4_req_bw_req(struct dc_link *link, int req_bw)
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/* Error check whether requested and allocated are equal */
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req_bw = requested_bw * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity);
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if (req_bw == link->dpia_bw_alloc_config.sink_allocated_bw) {
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if (req_bw == link->dpia_bw_alloc_config.allocated_bw) {
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DC_LOG_ERROR("%s: Request bw equals to allocated bw for link(%d)\n",
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__func__, link->link_index);
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}
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@ -387,9 +393,9 @@ void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t res
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DC_LOG_DEBUG("%s: BW REQ SUCCESS for DP-TX Request for link(%d)\n",
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__func__, link->link_index);
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DC_LOG_DEBUG("%s: current allocated_bw(%d), new allocated_bw(%d)\n",
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__func__, link->dpia_bw_alloc_config.sink_allocated_bw, bw_needed);
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__func__, link->dpia_bw_alloc_config.allocated_bw, bw_needed);
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link->dpia_bw_alloc_config.sink_allocated_bw = bw_needed;
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link->dpia_bw_alloc_config.allocated_bw = bw_needed;
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link->dpia_bw_alloc_config.response_ready = true;
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break;
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@ -427,8 +433,8 @@ int dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int pea
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if (link->hpd_status && peak_bw > 0) {
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// If DP over USB4 then we need to check BW allocation
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link->dpia_bw_alloc_config.sink_max_bw = peak_bw;
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set_usb4_req_bw_req(link, link->dpia_bw_alloc_config.sink_max_bw);
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link->dpia_bw_alloc_config.link_max_bw = peak_bw;
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set_usb4_req_bw_req(link, link->dpia_bw_alloc_config.link_max_bw);
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do {
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if (timeout > 0)
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@ -440,8 +446,8 @@ int dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int pea
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if (!timeout)
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ret = 0;// ERROR TIMEOUT waiting for response for allocating bw
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else if (link->dpia_bw_alloc_config.sink_allocated_bw > 0)
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ret = link->dpia_bw_alloc_config.sink_allocated_bw;
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else if (link->dpia_bw_alloc_config.allocated_bw > 0)
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ret = link->dpia_bw_alloc_config.allocated_bw;
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}
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//2. Cold Unplug
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else if (!link->hpd_status)
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@ -450,7 +456,6 @@ int dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int pea
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out:
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return ret;
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}
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bool link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw)
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{
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bool ret = false;
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@ -458,7 +463,7 @@ bool link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int r
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DC_LOG_DEBUG("%s: ENTER: link(%d), hpd_status(%d), current allocated_bw(%d), req_bw(%d)\n",
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__func__, link->link_index, link->hpd_status,
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link->dpia_bw_alloc_config.sink_allocated_bw, req_bw);
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link->dpia_bw_alloc_config.allocated_bw, req_bw);
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if (!get_bw_alloc_proceed_flag(link))
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goto out;
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@ -523,3 +528,29 @@ bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed_per_dpia, const
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return ret;
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}
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int link_dp_dpia_get_dp_overhead_in_dp_tunneling(struct dc_link *link)
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{
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int dp_overhead = 0, link_mst_overhead = 0;
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if (!get_bw_alloc_proceed_flag((link)))
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return dp_overhead;
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/* if its mst link, add MTPH overhead */
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if ((link->type == dc_connection_mst_branch) &&
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!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
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/* For 8b/10b encoding: MTP is 64 time slots long, slot 0 is used for MTPH
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* MST overhead is 1/64 of link bandwidth (excluding any overhead)
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*/
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const struct dc_link_settings *link_cap =
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dc_link_get_link_cap(link);
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uint32_t link_bw_in_kbps =
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link_cap->link_rate * link_cap->lane_count * LINK_RATE_REF_FREQ_IN_KHZ * 8;
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link_mst_overhead = (link_bw_in_kbps / 64) + ((link_bw_in_kbps % 64) ? 1 : 0);
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}
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/* add all the overheads */
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dp_overhead = link_mst_overhead;
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return dp_overhead;
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}
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@ -99,4 +99,13 @@ void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t res
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*/
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bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed, const unsigned int num_dpias);
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/*
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* Obtain all the DP overheads in dp tunneling for the dpia link
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*
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* @link: pointer to the dc_link struct instance
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*
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* return: DP overheads in DP tunneling
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*/
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int link_dp_dpia_get_dp_overhead_in_dp_tunneling(struct dc_link *link);
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#endif /* DC_INC_LINK_DP_DPIA_BW_H_ */
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