staging: mt7621-pci: handle phy using new generic phy 'pci-mt7621-phy' driver
Phy part of this driver has been moved to a new 'pci-mt7621-phy' driver. Change code to use kernel's generic phy API removing also no more need moved code. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sergio Paracuellos
Greg Kroah-Hartman
parent
00981d31d6
commit
61f9bde6ea
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@ -25,6 +25,7 @@
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <mt7621.h>
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@ -95,76 +96,12 @@
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#define RALINK_PCI_IO_MAP_BASE 0x1e160000
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#define MEMORY_BASE 0x0
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/* pcie phy related macros */
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#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
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#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
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#define RG_P0_TO_P1_WIDTH 0x100
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#define RG_PE1_PIPE_REG 0x02c
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#define RG_PE1_PIPE_RST BIT(12)
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#define RG_PE1_PIPE_CMD_FRC BIT(4)
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#define RG_PE1_H_LCDDS_REG 0x49c
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#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)
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#define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fffffff & (x)) << 0)
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#define RG_PE1_FRC_H_XTAL_REG 0x400
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#define RG_PE1_FRC_H_XTAL_TYPE BIT(8)
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#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9)
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#define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9)
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#define RG_PE1_FRC_PHY_REG 0x000
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#define RG_PE1_FRC_PHY_EN BIT(4)
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#define RG_PE1_PHY_EN BIT(5)
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#define RG_PE1_H_PLL_REG 0x490
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#define RG_PE1_H_PLL_BC GENMASK(23, 22)
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#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22)
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#define RG_PE1_H_PLL_BP GENMASK(21, 18)
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#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18)
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#define RG_PE1_H_PLL_IR GENMASK(15, 12)
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#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12)
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#define RG_PE1_H_PLL_IC GENMASK(11, 8)
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#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8)
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#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6)
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#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
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#define RG_PE1_PLL_DIVEN GENMASK(3, 1)
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#define RG_PE1_PLL_DIVEN_VAL(x) ((0x7 & (x)) << 1)
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#define RG_PE1_H_PLL_FBKSEL_REG 0x4bc
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#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4)
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#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4)
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#define RG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4
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#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0)
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#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x) ((0xffff & (x)) << 0)
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#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8
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#define RG_PE1_H_LCDDS_SSC_DELTA GENMASK(11, 0)
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#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0)
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#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16)
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#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
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#define RG_PE1_LCDDS_CLK_PH_INV_REG 0x4a0
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#define RG_PE1_LCDDS_CLK_PH_INV BIT(5)
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#define RG_PE1_H_PLL_BR_REG 0x4ac
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#define RG_PE1_H_PLL_BR GENMASK(18, 16)
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#define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16)
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#define RG_PE1_MSTCKDIV_REG 0x414
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#define RG_PE1_MSTCKDIV GENMASK(7, 6)
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#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6)
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#define RG_PE1_FRC_MSTCKDIV BIT(5)
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/**
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* struct mt7621_pcie_port - PCIe port information
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* @base: I/O mapped register base
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* @list: port list
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* @pcie: pointer to PCIe host info
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* @phy_reg_offset: offset to related phy registers
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* @phy: pointer to PHY control block
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* @pcie_rst: pointer to port reset control
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* @slot: port slot
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* @enabled: indicates if port is enabled
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@ -173,7 +110,7 @@ struct mt7621_pcie_port {
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void __iomem *base;
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struct list_head list;
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struct mt7621_pcie *pcie;
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u32 phy_reg_offset;
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struct phy *phy;
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struct reset_control *pcie_rst;
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u32 slot;
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bool enabled;
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@ -265,150 +202,6 @@ static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
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pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
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}
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static void bypass_pipe_rst(struct mt7621_pcie_port *port)
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{
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struct mt7621_pcie *pcie = port->pcie;
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u32 phy_offset = port->phy_reg_offset;
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u32 offset = (port->slot != 1) ?
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phy_offset + RG_PE1_PIPE_REG :
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phy_offset + RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH;
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u32 reg = pcie_read(pcie, offset);
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reg &= ~(RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
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reg |= (RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
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pcie_write(pcie, reg, offset);
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}
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static void set_phy_for_ssc(struct mt7621_pcie_port *port)
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{
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struct mt7621_pcie *pcie = port->pcie;
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struct device *dev = pcie->dev;
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u32 phy_offset = port->phy_reg_offset;
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u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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u32 offset;
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u32 val;
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reg = (reg >> 6) & 0x7;
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/* Set PCIe Port PHY to disable SSC */
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/* Debug Xtal Type */
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offset = phy_offset + RG_PE1_FRC_H_XTAL_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE);
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val |= RG_PE1_FRC_H_XTAL_TYPE;
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val |= RG_PE1_H_XTAL_TYPE_VAL(0x00);
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pcie_write(pcie, val, offset);
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/* disable port */
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offset = (port->slot != 1) ?
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phy_offset + RG_PE1_FRC_PHY_REG :
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phy_offset + RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
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val |= RG_PE1_FRC_PHY_EN;
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pcie_write(pcie, val, offset);
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/* Set Pre-divider ratio (for host mode) */
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offset = phy_offset + RG_PE1_H_PLL_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_H_PLL_PREDIV);
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if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
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val |= RG_PE1_H_PLL_PREDIV_VAL(0x01);
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pcie_write(pcie, val, offset);
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dev_info(dev, "Xtal is 40MHz\n");
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} else { /* 25MHz | 20MHz Xtal */
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val |= RG_PE1_H_PLL_PREDIV_VAL(0x00);
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pcie_write(pcie, val, offset);
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if (reg >= 6) {
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dev_info(dev, "Xtal is 25MHz\n");
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/* Select feedback clock */
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offset = phy_offset + RG_PE1_H_PLL_FBKSEL_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_H_PLL_FBKSEL);
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val |= RG_PE1_H_PLL_FBKSEL_VAL(0x01);
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pcie_write(pcie, val, offset);
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/* DDS NCPO PCW (for host mode) */
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offset = phy_offset + RG_PE1_H_LCDDS_SSC_PRD_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_H_LCDDS_SSC_PRD);
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val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000);
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pcie_write(pcie, val, offset);
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/* DDS SSC dither period control */
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offset = phy_offset + RG_PE1_H_LCDDS_SSC_PRD_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_H_LCDDS_SSC_PRD);
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val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d);
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pcie_write(pcie, val, offset);
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/* DDS SSC dither amplitude control */
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offset = phy_offset + RG_PE1_H_LCDDS_SSC_DELTA_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_H_LCDDS_SSC_DELTA |
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RG_PE1_H_LCDDS_SSC_DELTA1);
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val |= RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a);
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val |= RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a);
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pcie_write(pcie, val, offset);
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} else {
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dev_info(dev, "Xtal is 20MHz\n");
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}
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}
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/* DDS clock inversion */
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offset = phy_offset + RG_PE1_LCDDS_CLK_PH_INV_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_LCDDS_CLK_PH_INV);
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val |= RG_PE1_LCDDS_CLK_PH_INV;
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pcie_write(pcie, val, offset);
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/* Set PLL bits */
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offset = phy_offset + RG_PE1_H_PLL_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR |
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RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN);
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val |= RG_PE1_H_PLL_BC_VAL(0x02);
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val |= RG_PE1_H_PLL_BP_VAL(0x06);
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val |= RG_PE1_H_PLL_IR_VAL(0x02);
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val |= RG_PE1_H_PLL_IC_VAL(0x01);
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val |= RG_PE1_PLL_DIVEN_VAL(0x02);
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pcie_write(pcie, val, offset);
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offset = phy_offset + RG_PE1_H_PLL_BR_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_H_PLL_BR);
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val |= RG_PE1_H_PLL_BR_VAL(0x00);
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pcie_write(pcie, val, offset);
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if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
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/* set force mode enable of da_pe1_mstckdiv */
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offset = phy_offset + RG_PE1_MSTCKDIV_REG;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV);
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val |= (RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV);
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pcie_write(pcie, val, offset);
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}
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/* Enable PHY and disable force mode */
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offset = (port->slot != 1) ?
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phy_offset + RG_PE1_FRC_PHY_REG :
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phy_offset + RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
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val = pcie_read(pcie, offset);
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val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
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val |= (RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
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pcie_write(pcie, val, offset);
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}
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static void mt7621_enable_phy(struct mt7621_pcie_port *port)
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{
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u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
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if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
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bypass_pipe_rst(port);
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set_phy_for_ssc(port);
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}
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static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
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{
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u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
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@ -510,7 +303,7 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
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struct device *dev = pcie->dev;
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struct device_node *pnode = dev->of_node;
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struct resource regs;
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char name[6];
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char name[10];
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int err;
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port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
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@ -534,11 +327,13 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
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return PTR_ERR(port->pcie_rst);
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}
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snprintf(name, sizeof(name), "pcie-phy%d", slot);
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port->phy = devm_phy_get(dev, name);
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if (IS_ERR(port->phy))
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return PTR_ERR(port->phy);
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port->slot = slot;
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port->pcie = pcie;
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port->phy_reg_offset = (slot != 2) ?
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RALINK_PCIEPHY_P0P1_CTL_OFFSET :
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RALINK_PCIEPHY_P2_CTL_OFFSET;
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INIT_LIST_HEAD(&port->list);
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list_add_tail(&port->list, &pcie->ports);
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@ -588,6 +383,7 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
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struct device *dev = pcie->dev;
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u32 slot = port->slot;
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u32 val = 0;
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int err;
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/*
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* Any MT7621 Ralink pcie controller that doesn't have 0x0101 at
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@ -598,18 +394,36 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
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val = read_config(pcie, slot, PCIE_FTS_NUM);
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dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
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err = phy_init(port->phy);
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if (err) {
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dev_err(dev, "failed to initialize port%d phy\n", slot);
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goto err_phy_init;
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}
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err = phy_power_on(port->phy);
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if (err) {
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dev_err(dev, "failed to power on port%d phy\n", slot);
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goto err_phy_on;
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}
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if ((pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) == 0) {
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dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
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mt7621_control_assert(port);
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rt_sysc_m32(PCIE_PORT_CLK_EN(slot), 0, RALINK_CLKCFG1);
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port->enabled = false;
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} else {
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port->enabled = true;
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err = -ENODEV;
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goto err_no_link_up;
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}
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mt7621_enable_phy(port);
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port->enabled = true;
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return 0;
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err_no_link_up:
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phy_power_off(port->phy);
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err_phy_on:
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phy_exit(port->phy);
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err_phy_init:
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return err;
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}
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static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
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