rtw89: add chip_ops::{enable,disable}_bb_rf to support v1 chip
The v1 chip use specific functions to enable and disable BB/RF. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220325060055.58482-11-pkshih@realtek.com
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@ -2706,8 +2706,11 @@ int rtw89_core_start(struct rtw89_dev *rtwdev)
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/* efuse process */
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/* pre-config BB/RF, BB reset/RFC reset */
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rtw89_mac_disable_bb_rf(rtwdev);
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rtw89_mac_enable_bb_rf(rtwdev);
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rtw89_chip_disable_bb_rf(rtwdev);
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ret = rtw89_chip_enable_bb_rf(rtwdev);
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if (ret)
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return ret;
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rtw89_phy_init_bb_reg(rtwdev);
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rtw89_phy_init_rf_reg(rtwdev);
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@ -2059,6 +2059,8 @@ struct rtw89_hci_info {
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};
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struct rtw89_chip_ops {
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int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
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void (*disable_bb_rf)(struct rtw89_dev *rtwdev);
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void (*bb_reset)(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx);
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void (*bb_sethw)(struct rtw89_dev *rtwdev);
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@ -2828,7 +2828,7 @@ static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev)
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B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
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}
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void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
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int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
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{
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rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
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B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
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@ -2836,7 +2836,10 @@ void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
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B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
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B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
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rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
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return 0;
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}
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EXPORT_SYMBOL(rtw89_mac_enable_bb_rf);
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void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
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{
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@ -2847,6 +2850,7 @@ void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
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B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
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rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
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}
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EXPORT_SYMBOL(rtw89_mac_disable_bb_rf);
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int rtw89_mac_partial_init(struct rtw89_dev *rtwdev)
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{
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@ -2892,7 +2896,9 @@ int rtw89_mac_init(struct rtw89_dev *rtwdev)
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if (ret)
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goto fail;
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rtw89_mac_enable_bb_rf(rtwdev);
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ret = rtw89_chip_enable_bb_rf(rtwdev);
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if (ret)
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goto fail;
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ret = rtw89_mac_sys_init(rtwdev);
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if (ret)
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@ -797,8 +797,23 @@ int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
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int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
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int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
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int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
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void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
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int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
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void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
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static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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return chip->ops->enable_bb_rf(rtwdev);
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}
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static inline void rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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chip->ops->disable_bb_rf(rtwdev);
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}
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u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
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int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
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void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
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@ -903,6 +918,8 @@ int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
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struct rtw89_sta *rtwsta, u8 *tx_retry);
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enum rtw89_mac_xtal_si_offset {
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XTAL0 = 0x0,
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XTAL3 = 0x3,
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XTAL_SI_XTAL_SC_XI = 0x04,
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#define XTAL_SC_XI_MASK GENMASK(7, 0)
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XTAL_SI_XTAL_SC_XO = 0x05,
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@ -218,6 +218,7 @@
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#define B_AX_EECS_PULL_LOW_EN BIT(16)
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#define R_AX_WLRF_CTRL 0x02F0
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#define B_AX_AFC_AFEDIG BIT(17)
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#define B_AX_WLRF1_CTRL_7 BIT(15)
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#define B_AX_WLRF1_CTRL_1 BIT(9)
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#define B_AX_WLRF_CTRL_7 BIT(7)
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@ -231,6 +232,11 @@
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#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
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#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
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#define R_AX_AFE_OFF_CTRL1 0x0444
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#define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
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#define B_AX_S1_LDO2PWRCUT_F BIT(23)
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#define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
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#define R_AX_FILTER_MODEL_ADDR 0x0C04
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#define R_AX_HAXI_INIT_CFG1 0x1000
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@ -1997,6 +1997,8 @@ static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
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}
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static const struct rtw89_chip_ops rtw8852a_chip_ops = {
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.enable_bb_rf = rtw89_mac_enable_bb_rf,
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.disable_bb_rf = rtw89_mac_disable_bb_rf,
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.bb_reset = rtw8852a_bb_reset,
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.bb_sethw = rtw8852a_bb_sethw,
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.read_rf = rtw89_phy_read_rf,
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@ -483,7 +483,52 @@ void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
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}
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}
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static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
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{
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int ret;
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rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
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B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
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rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
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rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
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rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
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rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1);
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rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1);
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK);
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if (ret)
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return ret;
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ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK);
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if (ret)
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return ret;
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return 0;
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}
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static void rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
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{
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rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
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B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
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}
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static const struct rtw89_chip_ops rtw8852c_chip_ops = {
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.enable_bb_rf = rtw8852c_mac_enable_bb_rf,
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.disable_bb_rf = rtw8852c_mac_disable_bb_rf,
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.read_efuse = rtw8852c_read_efuse,
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.read_phycap = rtw8852c_read_phycap,
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.power_trim = rtw8852c_power_trim,
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