ARM: dts: imx7-tqma7: add SPI-NOR flash
The SPI-NOR flash on the SoM was missing from the device tree. The TQMa7 as a designated QSPI_RESET# pin, however depending on the hardware configuration the pin may be unconnected, or be used for a different purpose. With this in mind, we mux the pin as a pullup and define an input hog for it, but keep it a separate pin group, so that it is easy for dependent Device Trees to modify the configuration. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -19,6 +19,16 @@
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cpu-supply = <&sw1a_reg>;
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cpu-supply = <&sw1a_reg>;
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};
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};
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&gpio2 {
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/* Configured as pullup by QSPI pin group */
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qspi-reset-hog {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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input;
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line-name = "qspi-reset";
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};
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};
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&i2c1 {
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-0 = <&pinctrl_i2c1>;
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@ -160,6 +170,25 @@
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>;
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>;
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};
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A
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MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A
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MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A
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MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A
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MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11
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MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54
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MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54
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>;
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};
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pinctrl_qspi_reset: qspi_resetgrp {
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fsl,pins = <
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/* #QSPI_RESET */
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MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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fsl,pins = <
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MX7D_PAD_SD3_CMD__SD3_CMD 0x59
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MX7D_PAD_SD3_CMD__SD3_CMD 0x59
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@ -217,6 +246,20 @@
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};
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};
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};
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <29000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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};
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};
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&sdma {
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&sdma {
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status = "okay";
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status = "okay";
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};
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};
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