arm64: dts: mt8173: add MT8173 display PWM driver support node
Add display PWM node in mt8173-evb.dts and mt8173.dtsi. Signed-off-by: YH Huang <yh.huang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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@ -92,6 +92,13 @@
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};
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&pio {
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disp_pwm0_pins: disp_pwm0_pins {
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pins1 {
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pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
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output-low;
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};
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};
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mmc0_pins_default: mmc0default {
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pins_cmd_dat {
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pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
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@ -190,6 +197,12 @@
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};
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};
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&pwm0 {
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pinctrl-names = "default";
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pinctrl-0 = <&disp_pwm0_pins>;
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status = "okay";
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};
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&pwrap {
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pmic: mt6397 {
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compatible = "mediatek,mt6397";
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@ -525,6 +525,28 @@
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#clock-cells = <1>;
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};
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pwm0: pwm@1401e000 {
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compatible = "mediatek,mt8173-disp-pwm",
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"mediatek,mt6595-disp-pwm";
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reg = <0 0x1401e000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM026M>,
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<&mmsys CLK_MM_DISP_PWM0MM>;
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clock-names = "main", "mm";
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status = "disabled";
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};
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pwm1: pwm@1401f000 {
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compatible = "mediatek,mt8173-disp-pwm",
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"mediatek,mt6595-disp-pwm";
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reg = <0 0x1401f000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM126M>,
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<&mmsys CLK_MM_DISP_PWM1MM>;
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clock-names = "main", "mm";
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status = "disabled";
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};
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imgsys: clock-controller@15000000 {
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compatible = "mediatek,mt8173-imgsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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