media: atomisp: ov2680: Remove unnecessary registers from ov2680_global_setting[]
Many of the values in ov2680_global_setting[] match the default/reset register value for the ov2680 sensor (verified with both datasheet and actual hw) so they are no-ops. And there are also a couple of others which are later overwritten by ctrls or by ov2680_set_mode(). Remove all the unnecessary entries and add annotations to the remaining entries documenting what they change (in so far as things are documented in the datasheet). This also removes the double writing of OV2680_REG_SOFT_RESET in ov2680_init_registers() (one direct write, one in ov2680_global_setting[]) instead add a short sleep after the first write to give the sensor time to reset. Link: https://lore.kernel.org/r/20230604161406.69369-4-hdegoede@redhat.com Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Hans de Goede
Mauro Carvalho Chehab
parent
7d45a43225
commit
61ae5ec4c8
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@ -175,6 +175,10 @@ static int ov2680_init_registers(struct v4l2_subdev *sd)
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int ret;
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ret = ov_write_reg8(client, OV2680_SW_RESET, 0x01);
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/* Wait for sensor reset */
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usleep_range(1000, 2000);
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ret |= ov2680_write_reg_array(client, ov2680_global_setting);
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return ret;
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@ -172,82 +172,75 @@ static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
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}
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static struct ov2680_reg const ov2680_global_setting[] = {
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{0x0103, 0x01},
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{0x3002, 0x00},
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/* MIPI PHY, 0x10 -> 0x1c enable bp_c_hs_en_lat and bp_d_hs_en_lat */
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{0x3016, 0x1c},
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{0x3018, 0x44},
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{0x3020, 0x00},
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{0x3080, 0x02},
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/* PLL MULT bits 0-7, datasheet default 0x37 for 24MHz extclk, use 0x45 for 19.2 Mhz extclk */
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{0x3082, 0x45},
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{0x3084, 0x09},
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{0x3085, 0x04},
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{0x3086, 0x00},
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/* R MANUAL set exposure (0x01) and gain (0x02) to manual (hw does not do auto) */
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{0x3503, 0x03},
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{0x350b, 0x36},
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{0x3600, 0xb4},
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{0x3603, 0x39},
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{0x3604, 0x24},
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{0x3605, 0x00},
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{0x3620, 0x26},
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{0x3621, 0x37},
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{0x3622, 0x04},
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{0x3628, 0x00},
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{0x3705, 0x3c},
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{0x370c, 0x50},
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{0x370d, 0xc0},
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{0x3718, 0x88},
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{0x3720, 0x00},
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{0x3721, 0x00},
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{0x3722, 0x00},
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{0x3723, 0x00},
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{0x3738, 0x00},
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{0x3717, 0x58},
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{0x3781, 0x80},
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{0x3789, 0x60},
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{0x3800, 0x00},
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{0x3819, 0x04},
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/* Analog control register tweaks */
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{0x3603, 0x39}, /* Reset value 0x99 */
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{0x3604, 0x24}, /* Reset value 0x74 */
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{0x3621, 0x37}, /* Reset value 0x44 */
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/* Sensor control register tweaks */
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{0x3701, 0x64}, /* Reset value 0x61 */
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{0x3705, 0x3c}, /* Reset value 0x21 */
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{0x370c, 0x50}, /* Reset value 0x10 */
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{0x370d, 0xc0}, /* Reset value 0x00 */
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{0x3718, 0x88}, /* Reset value 0x80 */
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/* PSRAM tweaks */
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{0x3781, 0x80}, /* Reset value 0x00 */
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{0x3784, 0x0c}, /* Reset value 0x00, based on OV2680_R1A_AM10.ovt */
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{0x3789, 0x60}, /* Reset value 0x50 */
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/* BLC CTRL00 0x01 -> 0x81 set avg_weight to 8 */
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{0x4000, 0x81},
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{0x4001, 0x40},
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/* Set black level compensation range to 0 - 3 (default 0 - 11) */
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{0x4008, 0x00},
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{0x4009, 0x03},
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/* VFIFO R2 0x00 -> 0x02 set Frame reset enable */
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{0x4602, 0x02},
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/* MIPI ctrl CLK PREPARE MIN change from 0x26 (38) -> 0x36 (54) */
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{0x481f, 0x36},
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/* MIPI ctrl CLK LPX P MIN change from 0x32 (50) -> 0x36 (54) */
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{0x4825, 0x36},
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{0x4837, 0x18},
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/* R ISP CTRL2 0x20 -> 0x30, set sof_sel bit */
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{0x5002, 0x30},
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{0x5004, 0x04},//manual awb 1x
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{0x5005, 0x00},
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{0x5006, 0x04},
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{0x5007, 0x00},
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{0x5008, 0x04},
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{0x5009, 0x00},
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{0x5080, 0x00},
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{0x5081, 0x41},
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{0x5708, 0x01}, /* add for full size flip off and mirror off 2014/09/11 */
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{0x3701, 0x64}, //add on 14/05/13
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{0x3784, 0x0c}, //based OV2680_R1A_AM10.ovt add on 14/06/13
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{0x5780, 0x3e}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13
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{0x5781, 0x0f},
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{0x5782, 0x04},
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{0x5783, 0x02},
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{0x5784, 0x01},
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{0x5785, 0x01},
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{0x5786, 0x00},
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{0x5787, 0x04},
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/*
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* Window CONTROL 0x00 -> 0x01, enable manual window control,
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* this is necessary for full size flip and mirror support.
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*/
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{0x5708, 0x01},
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/*
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* DPC CTRL0 0x14 -> 0x3e, set enable_tail, enable_3x3_cluster
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* and enable_general_tail bits based OV2680_R1A_AM10.ovt.
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*/
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{0x5780, 0x3e},
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/* DPC MORE CONNECTION CASE THRE 0x0c (12) -> 0x02 (2) */
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{0x5788, 0x02},
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{0x5789, 0x00},
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{0x578a, 0x01},
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{0x578b, 0x02},
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{0x578c, 0x03},
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{0x578d, 0x03},
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/* DPC GAIN LIST1 0x0f (15) -> 0x08 (8) */
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{0x578e, 0x08},
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/* DPC GAIN LIST2 0x3f (63) -> 0x0c (12) */
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{0x578f, 0x0c},
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{0x5790, 0x08},
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{0x5791, 0x04},
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/* DPC THRE RATIO 0x04 (4) -> 0x00 (0) */
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{0x5792, 0x00},
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{0x5793, 0x00},
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{0x5794, 0x03}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13
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{0x0100, 0x00}, //stream off
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{}
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};
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