drm/amdgpu: update IH IV ring entry for soc-15
Reflect the new format on soc-15 asics. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -93,11 +93,14 @@ struct amdgpu_ih_ring {
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struct amdgpu_iv_entry {
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unsigned client_id;
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unsigned src_id;
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unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
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unsigned ring_id;
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unsigned vm_id;
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unsigned vm_id_src;
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uint64_t timestamp;
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unsigned timestamp_src;
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unsigned pas_id;
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unsigned pasid_src;
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unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
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const uint32_t *iv_entry;
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};
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