drm/nouveau/fifo/gk104: add nvdec plumbing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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9e4fff3205
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608fd040b7
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@ -11,6 +11,7 @@ struct kepler_channel_gpfifo_a_v0 {
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#define NVA06F_V0_ENGINE_MSPDEC 0x00000020
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#define NVA06F_V0_ENGINE_MSPDEC 0x00000020
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#define NVA06F_V0_ENGINE_MSPPP 0x00000040
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#define NVA06F_V0_ENGINE_MSPPP 0x00000040
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#define NVA06F_V0_ENGINE_MSENC 0x00000080
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#define NVA06F_V0_ENGINE_MSENC 0x00000080
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#define NVA06F_V0_ENGINE_NVDEC 0x00000200
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#define NVA06F_V0_ENGINE_NVENC0 0x00000400
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#define NVA06F_V0_ENGINE_NVENC0 0x00000400
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#define NVA06F_V0_ENGINE_NVENC1 0x00000800
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#define NVA06F_V0_ENGINE_NVENC1 0x00000800
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#define NVA06F_V0_ENGINE_CE0 0x00010000
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#define NVA06F_V0_ENGINE_CE0 0x00010000
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@ -737,6 +737,7 @@ gk104_fifo_oneinit(struct nvkm_fifo *base)
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case 0x0000000d: engidx = NVKM_ENGINE_SEC; break;
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case 0x0000000d: engidx = NVKM_ENGINE_SEC; break;
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case 0x0000000e: engidx = NVKM_ENGINE_NVENC0; break;
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case 0x0000000e: engidx = NVKM_ENGINE_NVENC0; break;
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case 0x0000000f: engidx = NVKM_ENGINE_NVENC1; break;
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case 0x0000000f: engidx = NVKM_ENGINE_NVENC1; break;
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case 0x00000010: engidx = NVKM_ENGINE_NVDEC; break;
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break;
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break;
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default:
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default:
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break;
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break;
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@ -67,6 +67,7 @@ gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
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case NVKM_ENGINE_MSPPP : return 0x0260;
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case NVKM_ENGINE_MSPPP : return 0x0260;
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case NVKM_ENGINE_MSVLD : return 0x0270;
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case NVKM_ENGINE_MSVLD : return 0x0270;
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case NVKM_ENGINE_MSENC : return 0x0290;
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case NVKM_ENGINE_MSENC : return 0x0290;
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case NVKM_ENGINE_NVDEC : return 0x02100270;
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case NVKM_ENGINE_NVENC0: return 0x02100290;
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case NVKM_ENGINE_NVENC0: return 0x02100290;
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case NVKM_ENGINE_NVENC1: return 0x0210;
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case NVKM_ENGINE_NVENC1: return 0x0210;
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default:
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default:
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@ -343,6 +344,7 @@ gk104_fifo_gpfifo[] = {
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{ NVA06F_V0_ENGINE_MSPDEC, BIT_ULL(NVKM_ENGINE_MSPDEC) },
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{ NVA06F_V0_ENGINE_MSPDEC, BIT_ULL(NVKM_ENGINE_MSPDEC) },
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{ NVA06F_V0_ENGINE_MSPPP , BIT_ULL(NVKM_ENGINE_MSPPP ) },
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{ NVA06F_V0_ENGINE_MSPPP , BIT_ULL(NVKM_ENGINE_MSPPP ) },
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{ NVA06F_V0_ENGINE_MSENC , BIT_ULL(NVKM_ENGINE_MSENC ) },
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{ NVA06F_V0_ENGINE_MSENC , BIT_ULL(NVKM_ENGINE_MSENC ) },
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{ NVA06F_V0_ENGINE_NVDEC , BIT_ULL(NVKM_ENGINE_NVDEC ) },
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{ NVA06F_V0_ENGINE_NVENC0, BIT_ULL(NVKM_ENGINE_NVENC0) },
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{ NVA06F_V0_ENGINE_NVENC0, BIT_ULL(NVKM_ENGINE_NVENC0) },
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{ NVA06F_V0_ENGINE_NVENC1, BIT_ULL(NVKM_ENGINE_NVENC1) },
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{ NVA06F_V0_ENGINE_NVENC1, BIT_ULL(NVKM_ENGINE_NVENC1) },
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{ NVA06F_V0_ENGINE_CE0 , BIT_ULL(NVKM_ENGINE_CE0 ) },
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{ NVA06F_V0_ENGINE_CE0 , BIT_ULL(NVKM_ENGINE_CE0 ) },
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