Mediatek DRM Fixes for Linux 5.15
1. Revert series "CMDQ refinement of Mediatek DRM driver" -----BEGIN PGP SIGNATURE----- iQJMBAABCgA2FiEEACwLKSDmq+9RDv5P4cpzo8lZTiQFAmFnbjIYHGNodW5rdWFu Zy5odUBrZXJuZWwub3JnAAoJEOHKc6PJWU4kAFMP/jfJmaJycW9vy8ZdVosU57fd uJu7Z/x0uJWBnGK93BGcC8OiHVR/3Bf35JVXECYbotZ2K6QXTj6GyT6K4fAU9V1e GA/9Jyq2fuYiI1uKErMUBsAJR1erZN+obFOvMD/QTK6nNJcoUiWbHHSwjrP+irY1 GidcAufvId2aFKUljTfVYEVGuGlR/DvN7XRl5ejp9pe0SyVno144NJOU2hKxV+WV cRi/2zbZQrpDdk/8xjHhLXUah54dk/lUAi8Sj3EGj3i/sp8UHRaCdzUHUI6+FUWj IkJiJqadvyF2kAOjX3W9p+AoxpkWT8na43+a+y7BUixwW88rkpbZJbzZPohr2Zp8 6dr2gXvZcRgyhUcjzS0A0HxbDw86zIXEyjC9HN86jM/ILqutVHTCipHPHAUIbOAp H/hTnsrDL+5E7xDrvcxhM3V9dpFNoewHvyemt1egdO9f/MjtVcx+24be3IdDb4Ur syr5WQAh6lB1HWd7i7dbz6v5ZoWiycVJoy0ylSiqJRa0hWT6elvkwwkf7ESP4IyE K9KEwEg7gVqQjisTUUdq0PYRsHIBa6Bx6HbuA3Tm/gIyQVLwMm9k/gGBVvB+9o85 azdHP1hyNotISZ7w2jOZ3Gzu804O8ZvV6UUKgBanJ+igwCJ1ChyBPaaq6k0cDa+Q PxeFHA1+9Aq3UIhPLvPf =A23A -----END PGP SIGNATURE----- Merge tag 'mediatek-drm-fixes-5.15' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes Mediatek DRM Fixes for Linux 5.15 1. Revert series "CMDQ refinement of Mediatek DRM driver" Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20211013235044.5488-1-chunkuang.hu@kernel.org
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commit
6011106d12
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@ -4,8 +4,6 @@
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/mailbox_controller.h>
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#include <linux/pm_runtime.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include <linux/soc/mediatek/mtk-mmsys.h>
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@ -52,11 +50,8 @@ struct mtk_drm_crtc {
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bool pending_async_planes;
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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struct mbox_client cmdq_cl;
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struct mbox_chan *cmdq_chan;
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struct cmdq_pkt cmdq_handle;
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struct cmdq_client *cmdq_client;
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u32 cmdq_event;
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u32 cmdq_vblank_cnt;
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#endif
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struct device *mmsys_dev;
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@ -227,79 +222,9 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
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}
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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static int mtk_drm_cmdq_pkt_create(struct mbox_chan *chan, struct cmdq_pkt *pkt,
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size_t size)
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static void ddp_cmdq_cb(struct cmdq_cb_data data)
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{
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struct device *dev;
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dma_addr_t dma_addr;
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pkt->va_base = kzalloc(size, GFP_KERNEL);
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if (!pkt->va_base) {
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kfree(pkt);
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return -ENOMEM;
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}
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pkt->buf_size = size;
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dev = chan->mbox->dev;
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dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, dma_addr)) {
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dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
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kfree(pkt->va_base);
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kfree(pkt);
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return -ENOMEM;
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}
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pkt->pa_base = dma_addr;
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return 0;
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}
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static void mtk_drm_cmdq_pkt_destroy(struct mbox_chan *chan, struct cmdq_pkt *pkt)
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{
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dma_unmap_single(chan->mbox->dev, pkt->pa_base, pkt->buf_size,
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DMA_TO_DEVICE);
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kfree(pkt->va_base);
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kfree(pkt);
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}
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static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
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{
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struct mtk_drm_crtc *mtk_crtc = container_of(cl, struct mtk_drm_crtc, cmdq_cl);
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struct cmdq_cb_data *data = mssg;
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struct mtk_crtc_state *state;
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unsigned int i;
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state = to_mtk_crtc_state(mtk_crtc->base.state);
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state->pending_config = false;
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if (mtk_crtc->pending_planes) {
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for (i = 0; i < mtk_crtc->layer_nr; i++) {
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struct drm_plane *plane = &mtk_crtc->planes[i];
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struct mtk_plane_state *plane_state;
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plane_state = to_mtk_plane_state(plane->state);
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plane_state->pending.config = false;
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}
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mtk_crtc->pending_planes = false;
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}
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if (mtk_crtc->pending_async_planes) {
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for (i = 0; i < mtk_crtc->layer_nr; i++) {
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struct drm_plane *plane = &mtk_crtc->planes[i];
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struct mtk_plane_state *plane_state;
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plane_state = to_mtk_plane_state(plane->state);
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plane_state->pending.async_config = false;
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}
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mtk_crtc->pending_async_planes = false;
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}
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mtk_crtc->cmdq_vblank_cnt = 0;
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mtk_drm_cmdq_pkt_destroy(mtk_crtc->cmdq_chan, data->pkt);
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cmdq_pkt_destroy(data.data);
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}
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#endif
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@ -453,8 +378,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
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state->pending_vrefresh, 0,
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cmdq_handle);
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if (!cmdq_handle)
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state->pending_config = false;
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state->pending_config = false;
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}
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if (mtk_crtc->pending_planes) {
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@ -474,12 +398,9 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
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mtk_ddp_comp_layer_config(comp, local_layer,
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plane_state,
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cmdq_handle);
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if (!cmdq_handle)
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plane_state->pending.config = false;
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plane_state->pending.config = false;
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}
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if (!cmdq_handle)
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mtk_crtc->pending_planes = false;
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mtk_crtc->pending_planes = false;
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}
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if (mtk_crtc->pending_async_planes) {
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@ -499,12 +420,9 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
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mtk_ddp_comp_layer_config(comp, local_layer,
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plane_state,
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cmdq_handle);
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if (!cmdq_handle)
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plane_state->pending.async_config = false;
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plane_state->pending.async_config = false;
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}
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if (!cmdq_handle)
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mtk_crtc->pending_async_planes = false;
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mtk_crtc->pending_async_planes = false;
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}
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}
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@ -512,7 +430,7 @@ static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
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bool needs_vblank)
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{
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
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struct cmdq_pkt *cmdq_handle;
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#endif
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struct drm_crtc *crtc = &mtk_crtc->base;
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struct mtk_drm_private *priv = crtc->dev->dev_private;
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mtk_mutex_release(mtk_crtc->mutex);
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}
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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if (mtk_crtc->cmdq_chan) {
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mbox_flush(mtk_crtc->cmdq_chan, 2000);
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cmdq_handle->cmd_buf_size = 0;
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if (mtk_crtc->cmdq_client) {
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mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
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cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
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cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
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cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
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mtk_crtc_ddp_config(crtc, cmdq_handle);
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cmdq_pkt_finalize(cmdq_handle);
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dma_sync_single_for_device(mtk_crtc->cmdq_chan->mbox->dev,
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cmdq_handle->pa_base,
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cmdq_handle->cmd_buf_size,
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DMA_TO_DEVICE);
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/*
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* CMDQ command should execute in next vblank,
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* If it fail to execute in next 2 vblank, timeout happen.
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*/
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mtk_crtc->cmdq_vblank_cnt = 2;
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mbox_send_message(mtk_crtc->cmdq_chan, cmdq_handle);
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mbox_client_txdone(mtk_crtc->cmdq_chan, 0);
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cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
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}
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#endif
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mtk_crtc->config_updating = false;
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struct mtk_drm_private *priv = crtc->dev->dev_private;
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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if (!priv->data->shadow_register && !mtk_crtc->cmdq_chan)
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mtk_crtc_ddp_config(crtc, NULL);
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else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
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DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
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drm_crtc_index(&mtk_crtc->base));
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if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)
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#else
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if (!priv->data->shadow_register)
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mtk_crtc_ddp_config(crtc, NULL);
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#endif
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mtk_crtc_ddp_config(crtc, NULL);
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mtk_drm_finish_page_flip(mtk_crtc);
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}
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mutex_init(&mtk_crtc->hw_lock);
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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mtk_crtc->cmdq_cl.dev = mtk_crtc->mmsys_dev;
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mtk_crtc->cmdq_cl.tx_block = false;
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mtk_crtc->cmdq_cl.knows_txdone = true;
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mtk_crtc->cmdq_cl.rx_callback = ddp_cmdq_cb;
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mtk_crtc->cmdq_chan =
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mbox_request_channel(&mtk_crtc->cmdq_cl,
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drm_crtc_index(&mtk_crtc->base));
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if (IS_ERR(mtk_crtc->cmdq_chan)) {
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mtk_crtc->cmdq_client =
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cmdq_mbox_create(mtk_crtc->mmsys_dev,
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drm_crtc_index(&mtk_crtc->base));
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if (IS_ERR(mtk_crtc->cmdq_client)) {
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dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
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drm_crtc_index(&mtk_crtc->base));
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mtk_crtc->cmdq_chan = NULL;
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mtk_crtc->cmdq_client = NULL;
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}
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if (mtk_crtc->cmdq_chan) {
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if (mtk_crtc->cmdq_client) {
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ret = of_property_read_u32_index(priv->mutex_node,
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"mediatek,gce-events",
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drm_crtc_index(&mtk_crtc->base),
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if (ret) {
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dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
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drm_crtc_index(&mtk_crtc->base));
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mbox_free_channel(mtk_crtc->cmdq_chan);
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mtk_crtc->cmdq_chan = NULL;
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} else {
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ret = mtk_drm_cmdq_pkt_create(mtk_crtc->cmdq_chan,
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&mtk_crtc->cmdq_handle,
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PAGE_SIZE);
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if (ret) {
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dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
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drm_crtc_index(&mtk_crtc->base));
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mbox_free_channel(mtk_crtc->cmdq_chan);
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mtk_crtc->cmdq_chan = NULL;
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}
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cmdq_mbox_destroy(mtk_crtc->cmdq_client);
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mtk_crtc->cmdq_client = NULL;
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}
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}
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#endif
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