UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

Allwinner SoC support for 3.8 

-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iEYEABECAAYFAlCmwSAACgkQGxsu9jQV9nbssgCcChzwuFlPkP4sVdTtAGGh5mWD
 rNcAn3PfG1ByMR57GkDtdQiAjS5N2dME
 =Pi49
 -----END PGP SIGNATURE-----

Merge tag 'tags/sunxi-support-for-3.8' of git://github.com/mripard/linux into next/soc

From Maxime Ripard:
Allwinner SoC support for 3.8

* tag 'tags/sunxi-support-for-3.8' of git://github.com/mripard/linux:
  ARM: sunxi: Add entry to MAINTAINERS
  ARM: sunxi: Add device tree for the A13 and the Olinuxino board
  ARM: sunxi: Add earlyprintk support
  ARM: sunxi: Add basic support for Allwinner A1x SoCs
  irqchip: sunxi: Add irq controller driver
  clocksource: sunxi: Add Allwinner A1X Timer Driver
  clk: sunxi: Add dummy fixed rate clock for Allwinner A1X SoCs

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2012-11-20 22:14:59 -08:00
parent 8ac49e0485 1b10669964
commit 5ffd785402
26 changed files with 802 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
Documentation/arm/sunxi/README Normal file
View File

@ -0,0 +1,19 @@
ARM Allwinner SoCs
==================
This document lists all the ARM Allwinner SoCs that are currently
supported in mainline by the Linux kernel. This document will also
provide links to documentation and or datasheet for these SoCs.
SunXi family
------------
Flavors:
Allwinner A10 (sun4i)
Datasheet : http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
Allwinner A13 (sun5i)
Datasheet : http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
Core: Cortex A8
Linux kernel mach directory: arch/arm/mach-sunxi

104
Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt Normal file
View File

@ -0,0 +1,104 @@
Allwinner Sunxi Interrupt Controller
Required properties:
- compatible : should be "allwinner,sunxi-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
The interrupt sources are as follows:
0: ENMI
1: UART0
2: UART1
3: UART2
4: UART3
5: IR0
6: IR1
7: I2C0
8: I2C1
9: I2C2
10: SPI0
11: SPI1
12: SPI2
13: SPDIF
14: AC97
15: TS
16: I2S
17: UART4
18: UART5
19: UART6
20: UART7
21: KEYPAD
22: TIMER0
23: TIMER1
24: TIMER2
25: TIMER3
26: CAN
27: DMA
28: PIO
29: TOUCH_PANEL
30: AUDIO_CODEC
31: LRADC
32: SDMC0
33: SDMC1
34: SDMC2
35: SDMC3
36: MEMSTICK
37: NAND
38: USB0
39: USB1
40: USB2
41: SCR
42: CSI0
43: CSI1
44: LCDCTRL0
45: LCDCTRL1
46: MP
47: DEFEBE0
48: DEFEBE1
49: PMU
50: SPI3
51: TZASC
52: PATA
53: VE
54: SS
55: EMAC
56: SATA
57: GPS
58: HDMI
59: TVE
60: ACE
61: TVD
62: PS2_0
63: PS2_1
64: USB3
65: USB4
66: PLE_PFM
67: TIMER4
68: TIMER5
69: GPU_GP
70: GPU_GPMMU
71: GPU_PP0
72: GPU_PPMMU0
73: GPU_PMU
74: GPU_RSV0
75: GPU_RSV1
76: GPU_RSV2
77: GPU_RSV3
78: GPU_RSV4
79: GPU_RSV5
80: GPU_RSV6
82: SYNC_TIMER0
83: SYNC_TIMER1
Example:
intc: interrupt-controller {
compatible = "allwinner,sunxi-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <2>;
};

17
Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt Normal file
View File

@ -0,0 +1,17 @@
Allwinner A1X SoCs Timer Controller
Required properties:
- compatible : should be "allwinner,sunxi-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The interrupt of the first timer
- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
Example:
timer {
compatible = "allwinner,sunxi-timer";
reg = <0x01c20c00 0x400>;
interrupts = <22>;
clocks = <&osc>;
};

6
MAINTAINERS
View File

@ -685,6 +685,12 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/Allwinner A1X SoC support
M: Maxime Ripard <maxime.ripard@free-electrons.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-sunxi/
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
M: Andrew Victor <linux@maxim.org.za>
M: Nicolas Ferre <nicolas.ferre@atmel.com>

2
arch/arm/Kconfig
View File

@ -1102,6 +1102,8 @@ source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/mach-shmobile/Kconfig"
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-prima2/Kconfig"
source "arch/arm/mach-tegra/Kconfig"

8
arch/arm/Kconfig.debug
View File

@ -345,6 +345,13 @@ choice
Say Y here if you want kernel low-level debugging support
on SOCFPGA based platforms.
config DEBUG_SUNXI_UART1
bool "Kernel low-level debugging messages via sunXi UART1"
depends on ARCH_SUNXI
help
Say Y here if you want kernel low-level debugging support
on Allwinner A1X based platforms on the UART1.
config DEBUG_VEXPRESS_UART0_DETECT
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
depends on ARCH_VEXPRESS && CPU_CP15_MMU
@ -424,6 +431,7 @@ config DEBUG_LL_INCLUDE
default "debug/mvebu.S" if DEBUG_MVEBU_UART
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
default "debug/sunxi.S" if DEBUG_SUNXI_UART1
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
default "mach/debug-macro.S"

1
arch/arm/Makefile
View File

@ -194,6 +194,7 @@ machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx
machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx
machine-$(CONFIG_MACH_SPEAR600) += spear6xx
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_SUNXI) += sunxi
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.

1
arch/arm/boot/dts/Makefile
View File

@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear310-evb.dtb \
spear320-evb.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun5i-olinuxino.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \

26
arch/arm/boot/dts/sun5i-olinuxino.dts Normal file
View File

@ -0,0 +1,26 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun5i.dtsi"
/ {
model = "Olimex A13-Olinuxino";
compatible = "olimex,a13-olinuxino", "allwinner,sun5i";
soc {
duart: uart@01c28400 {
status = "okay";
};
};
};

74
arch/arm/boot/dts/sun5i.dtsi Normal file
View File

@ -0,0 +1,74 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&intc>;
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
};
};
chosen {
bootargs = "earlyprintk console=ttyS0,115200";
};
memory {
reg = <0x40000000 0x20000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x01c20000 0x300000>;
ranges;
timer@01c20c00 {
compatible = "allwinner,sunxi-timer";
reg = <0x01c20c00 0x400>;
interrupts = <22>;
clocks = <&osc>;
};
intc: interrupt-controller@01c20400 {
compatible = "allwinner,sunxi-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
uart1: uart@01c28400 {
compatible = "ns8250";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
clock-frequency = <24000000>;
status = "disabled";
};
};
};

24
arch/arm/include/debug/sunxi.S Normal file
View File

@ -0,0 +1,24 @@
/*
* Early serial output macro for Allwinner A1X SoCs
*
* Copyright (C) 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef CONFIG_DEBUG_SUNXI_UART1
#define SUNXI_UART_DEBUG_PHYS_BASE 0x01c28400
#define SUNXI_UART_DEBUG_VIRT_BASE 0xf1c28400
#endif
.macro addruart, rp, rv, tmp
ldr \rp, =SUNXI_UART_DEBUG_PHYS_BASE
ldr \rv, =SUNXI_UART_DEBUG_VIRT_BASE
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

9
arch/arm/mach-sunxi/Kconfig Normal file
View File

@ -0,0 +1,9 @@
config ARCH_SUNXI
bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
select CLKSRC_MMIO
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select PINCTRL
select SPARSE_IRQ
select SUNXI_TIMER

1
arch/arm/mach-sunxi/Makefile Normal file
View File

@ -0,0 +1 @@
obj-$(CONFIG_ARCH_SUNXI) += sunxi.o

1
arch/arm/mach-sunxi/Makefile.boot Normal file
View File

@ -0,0 +1 @@
zreladdr-$(CONFIG_ARCH_SUNXI) += 0x40008000

60
arch/arm/mach-sunxi/sunxi.c Normal file
View File

@ -0,0 +1,60 @@
/*
* Device Tree support for Allwinner A1X SoCs
*
* Copyright (C) 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/sunxi_timer.h>
#include <linux/irqchip/sunxi.h>
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "sunxi.h"
static struct map_desc sunxi_io_desc[] __initdata = {
{
.virtual = (unsigned long) SUNXI_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
.length = SUNXI_REGS_SIZE,
.type = MT_DEVICE,
},
};
void __init sunxi_map_io(void)
{
iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
}
static void __init sunxi_dt_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const sunxi_board_dt_compat[] = {
"allwinner,sun5i",
NULL,
};
DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
.init_machine = sunxi_dt_init,
.map_io = sunxi_map_io,
.init_irq = sunxi_init_irq,
.handle_irq = sunxi_handle_irq,
.timer = &sunxi_timer,
.dt_compat = sunxi_board_dt_compat,
MACHINE_END

20
arch/arm/mach-sunxi/sunxi.h Normal file
View File

@ -0,0 +1,20 @@
/*
* Generic definitions for Allwinner SunXi SoCs
*
* Copyright (C) 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_SUNXI_H
#define __MACH_SUNXI_H
#define SUNXI_REGS_PHYS_BASE 0x01c00000
#define SUNXI_REGS_VIRT_BASE IOMEM(0xf1c00000)
#define SUNXI_REGS_SIZE (SZ_2M + SZ_1M)
#endif /* __MACH_SUNXI_H */

1
drivers/clk/Makefile
View File

@ -19,6 +19,7 @@ endif
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
# Chip specific
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o

30
drivers/clk/clk-sunxi.c Normal file
View File

@ -0,0 +1,30 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/sunxi.h>
#include <linux/of.h>
static const __initconst struct of_device_id clk_match[] = {
{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
{}
};
void __init sunxi_init_clocks(void)
{
of_clk_init(clk_match);
}

3
drivers/clocksource/Kconfig
View File

@ -22,6 +22,9 @@ config DW_APB_TIMER_OF
config ARMADA_370_XP_TIMER
bool
config SUNXI_TIMER
bool
config CLKSRC_DBX500_PRCMU
bool "Clocksource PRCMU Timer"
depends on UX500_SOC_DB8500

1
drivers/clocksource/Makefile
View File

@ -14,5 +14,6 @@ obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
obj-$(CONFIG_CLKSRC_ARM_GENERIC) += arm_generic.o

170
drivers/clocksource/sunxi_timer.c Normal file
View File

@ -0,0 +1,170 @@
/*
* Allwinner A1X SoCs timer handling.
*
* Copyright (C) 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* Based on code from
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Benn Huang <benn@allwinnertech.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sunxi_timer.h>
#include <linux/clk/sunxi.h>
#define TIMER_CTL_REG 0x00
#define TIMER_CTL_ENABLE (1 << 0)
#define TIMER_IRQ_ST_REG 0x04
#define TIMER0_CTL_REG 0x10
#define TIMER0_CTL_ENABLE (1 << 0)
#define TIMER0_CTL_AUTORELOAD (1 << 1)
#define TIMER0_CTL_ONESHOT (1 << 7)
#define TIMER0_INTVAL_REG 0x14
#define TIMER0_CNTVAL_REG 0x18
#define TIMER_SCAL 16
static void __iomem *timer_base;
static void sunxi_clkevt_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
u32 u = readl(timer_base + TIMER0_CTL_REG);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
u &= ~(TIMER0_CTL_ONESHOT);
writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
break;
case CLOCK_EVT_MODE_ONESHOT:
writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
break;
}
}
static int sunxi_clkevt_next_event(unsigned long evt,
struct clock_event_device *unused)
{
u32 u = readl(timer_base + TIMER0_CTL_REG);
writel(evt, timer_base + TIMER0_CNTVAL_REG);
writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
timer_base + TIMER0_CTL_REG);
return 0;
}
static struct clock_event_device sunxi_clockevent = {
.name = "sunxi_tick",
.shift = 32,
.rating = 300,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = sunxi_clkevt_mode,
.set_next_event = sunxi_clkevt_next_event,
};
static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = (struct clock_event_device *)dev_id;
writel(0x1, timer_base + TIMER_IRQ_ST_REG);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction sunxi_timer_irq = {
.name = "sunxi_timer0",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = sunxi_timer_interrupt,
.dev_id = &sunxi_clockevent,
};
static struct of_device_id sunxi_timer_dt_ids[] = {
{ .compatible = "allwinner,sunxi-timer" },
};
static void __init sunxi_timer_init(void)
{
struct device_node *node;
unsigned long rate = 0;
struct clk *clk;
int ret, irq;
u32 val;
node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
if (!node)
panic("No sunxi timer node");
timer_base = of_iomap(node, 0);
if (!timer_base)
panic("Can't map registers");
irq = irq_of_parse_and_map(node, 0);
if (irq <= 0)
panic("Can't parse IRQ");
sunxi_init_clocks();
clk = of_clk_get(node, 0);
if (IS_ERR(clk))
panic("Can't get timer clock");
rate = clk_get_rate(clk);
writel(rate / (TIMER_SCAL * HZ),
timer_base + TIMER0_INTVAL_REG);
/* set clock source to HOSC, 16 pre-division */
val = readl(timer_base + TIMER0_CTL_REG);
val &= ~(0x07 << 4);
val &= ~(0x03 << 2);
val |= (4 << 4) | (1 << 2);
writel(val, timer_base + TIMER0_CTL_REG);
/* set mode to auto reload */
val = readl(timer_base + TIMER0_CTL_REG);
writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
ret = setup_irq(irq, &sunxi_timer_irq);
if (ret)
pr_warn("failed to setup irq %d\n", irq);
/* Enable timer0 interrupt */
val = readl(timer_base + TIMER_CTL_REG);
writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
sunxi_clockevent.mult = div_sc(rate / TIMER_SCAL,
NSEC_PER_SEC,
sunxi_clockevent.shift);
sunxi_clockevent.max_delta_ns = clockevent_delta2ns(0xff,
&sunxi_clockevent);
sunxi_clockevent.min_delta_ns = clockevent_delta2ns(0x1,
&sunxi_clockevent);
sunxi_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&sunxi_clockevent);
}
struct sys_timer sunxi_timer = {
.init = sunxi_timer_init,
};

1
drivers/irqchip/Makefile
View File

@ -1,2 +1,3 @@
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o

150
drivers/irqchip/irq-sunxi.c Normal file
View File

@ -0,0 +1,150 @@
/*
* Allwinner A1X SoCs IRQ chip driver.
*
* Copyright (C) 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* Based on code from
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Benn Huang <benn@allwinnertech.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqchip/sunxi.h>
#define SUNXI_IRQ_VECTOR_REG 0x00
#define SUNXI_IRQ_PROTECTION_REG 0x08
#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
static void __iomem *sunxi_irq_base;
static struct irq_domain *sunxi_irq_domain;
void sunxi_irq_ack(struct irq_data *irqd)
{
unsigned int irq = irqd_to_hwirq(irqd);
unsigned int irq_off = irq % 32;
int reg = irq / 32;
u32 val;
val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
writel(val | (1 << irq_off),
sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
}
static void sunxi_irq_mask(struct irq_data *irqd)
{
unsigned int irq = irqd_to_hwirq(irqd);
unsigned int irq_off = irq % 32;
int reg = irq / 32;
u32 val;
val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
writel(val & ~(1 << irq_off),
sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
}
static void sunxi_irq_unmask(struct irq_data *irqd)
{
unsigned int irq = irqd_to_hwirq(irqd);
unsigned int irq_off = irq % 32;
int reg = irq / 32;
u32 val;
val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
writel(val | (1 << irq_off),
sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
}
static struct irq_chip sunxi_irq_chip = {
.name = "sunxi_irq",
.irq_ack = sunxi_irq_ack,
.irq_mask = sunxi_irq_mask,
.irq_unmask = sunxi_irq_unmask,
};
static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw)
{
irq_set_chip_and_handler(virq, &sunxi_irq_chip,
handle_level_irq);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
return 0;
}
static struct irq_domain_ops sunxi_irq_ops = {
.map = sunxi_irq_map,
.xlate = irq_domain_xlate_onecell,
};
static int __init sunxi_of_init(struct device_node *node,
struct device_node *parent)
{
sunxi_irq_base = of_iomap(node, 0);
if (!sunxi_irq_base)
panic("%s: unable to map IC registers\n",
node->full_name);
/* Disable all interrupts */
writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
/* Mask all the interrupts */
writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
/* Clear all the pending interrupts */
writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
/* Enable protection mode */
writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
/* Configure the external interrupt source type */
writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
&sunxi_irq_ops, NULL);
if (!sunxi_irq_domain)
panic("%s: unable to create IRQ domain\n", node->full_name);
return 0;
}
static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
{ .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init }
};
void __init sunxi_init_irq(void)
{
of_irq_init(sunxi_irq_dt_ids);
}
asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
{
u32 irq, hwirq;
hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
while (hwirq != 0) {
irq = irq_find_mapping(sunxi_irq_domain, hwirq);
handle_IRQ(irq, regs);
hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
}
}

22
include/linux/clk/sunxi.h Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_CLK_SUNXI_H_
#define __LINUX_CLK_SUNXI_H_
void __init sunxi_init_clocks(void);
#endif

27
include/linux/irqchip/sunxi.h Normal file
View File

@ -0,0 +1,27 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_IRQCHIP_SUNXI_H
#define __LINUX_IRQCHIP_SUNXI_H
#include <asm/exception.h>
extern void sunxi_init_irq(void);
extern asmlinkage void __exception_irq_entry sunxi_handle_irq(
struct pt_regs *regs);
#endif

24
include/linux/sunxi_timer.h Normal file
View File

@ -0,0 +1,24 @@
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SUNXI_TIMER_H
#define __SUNXI_TIMER_H
#include <asm/mach/time.h>
extern struct sys_timer sunxi_timer;
#endif