[POWERPC] 4xx: Fix PESDRn_UTLSET1 register setup on 460EX/GT
The patch fixes a bug, where the PESDRn_UTLSET1 register was setup wrongly resulting in a non working PCIe port 1. With this fix both PCIe ports work fine again. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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@ -785,19 +785,17 @@ static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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u32 val;
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u32 utlset1;
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if (port->endpoint) {
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if (port->endpoint)
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val = PTYPE_LEGACY_ENDPOINT << 20;
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utlset1 = 0x20222222;
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} else {
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else
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val = PTYPE_ROOT_PORT << 20;
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utlset1 = 0x21222222;
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}
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if (port->index == 0) {
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val |= LNKW_X1 << 12;
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utlset1 = 0x20000000;
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} else {
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val |= LNKW_X4 << 12;
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utlset1 |= 0x00101101;
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utlset1 = 0x20101101;
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}
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mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
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