soc/tegra: pmc: Add sysfs entries for reset info
Implement read-only reset_reason and reset_level sysfs attributes that can be used to query the reset reason and level at runtime. Signed-off-by: Sandipan Patra <spatra@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Sandipan Patra
Thierry Reding
parent
3bb2f843c0
commit
5f84bb1a40
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@ -2,6 +2,7 @@
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* drivers/soc/tegra/pmc.c
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*
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* Copyright (c) 2010 Google, Inc
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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@ -92,7 +93,6 @@
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#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
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#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
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#define PMC_RST_STATUS 0x1b4
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#define PMC_RST_STATUS_POR 0
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#define PMC_RST_STATUS_WATCHDOG 1
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#define PMC_RST_STATUS_SENSOR 2
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@ -151,6 +151,11 @@ struct tegra_pmc_regs {
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unsigned int dpd_status;
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unsigned int dpd2_req;
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unsigned int dpd2_status;
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unsigned int rst_status;
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unsigned int rst_source_shift;
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unsigned int rst_source_mask;
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unsigned int rst_level_shift;
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unsigned int rst_level_mask;
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};
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struct tegra_pmc_soc {
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@ -175,6 +180,42 @@ struct tegra_pmc_soc {
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void (*setup_irq_polarity)(struct tegra_pmc *pmc,
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struct device_node *np,
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bool invert);
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const char * const *reset_sources;
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unsigned int num_reset_sources;
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const char * const *reset_levels;
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unsigned int num_reset_levels;
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};
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static const char * const tegra186_reset_sources[] = {
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"SYS_RESET",
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"AOWDT",
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"MCCPLEXWDT",
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"BPMPWDT",
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"SCEWDT",
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"SPEWDT",
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"APEWDT",
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"BCCPLEXWDT",
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"SENSOR",
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"AOTAG",
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"VFSENSOR",
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"SWREST",
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"SC7",
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"HSM",
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"CORESIGHT"
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};
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static const char * const tegra186_reset_levels[] = {
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"L0", "L1", "L2", "WARM"
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};
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static const char * const tegra30_reset_sources[] = {
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"POWER_ON_RESET",
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"WATCHDOG",
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"SENSOR",
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"SW_MAIN",
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"LP0",
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"AOTAG"
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};
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/**
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@ -1527,6 +1568,56 @@ static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
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return err;
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}
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static ssize_t reset_reason_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 value, rst_src;
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value = tegra_pmc_readl(pmc->soc->regs->rst_status);
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rst_src = (value & pmc->soc->regs->rst_source_mask) >>
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pmc->soc->regs->rst_source_shift;
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return sprintf(buf, "%s\n", pmc->soc->reset_sources[rst_src]);
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}
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static DEVICE_ATTR_RO(reset_reason);
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static ssize_t reset_level_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 value, rst_lvl;
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value = tegra_pmc_readl(pmc->soc->regs->rst_status);
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rst_lvl = (value & pmc->soc->regs->rst_level_mask) >>
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pmc->soc->regs->rst_level_shift;
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return sprintf(buf, "%s\n", pmc->soc->reset_levels[rst_lvl]);
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}
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static DEVICE_ATTR_RO(reset_level);
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static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
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{
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struct device *dev = pmc->dev;
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int err = 0;
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if (pmc->soc->reset_sources) {
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err = device_create_file(dev, &dev_attr_reset_reason);
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if (err < 0)
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dev_warn(dev,
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"failed to create attr \"reset_reason\": %d\n",
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err);
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}
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if (pmc->soc->reset_levels) {
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err = device_create_file(dev, &dev_attr_reset_level);
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if (err < 0)
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dev_warn(dev,
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"failed to create attr \"reset_level\": %d\n",
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err);
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}
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}
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static int tegra_pmc_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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@ -1596,6 +1687,8 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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tegra_pmc_init_tsense_reset(pmc);
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tegra_pmc_reset_sysfs_init(pmc);
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if (IS_ENABLED(CONFIG_DEBUG_FS)) {
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err = tegra_powergate_debugfs_init();
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if (err < 0)
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@ -1662,6 +1755,11 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = {
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.dpd_status = 0x1bc,
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.dpd2_req = 0x1c0,
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.dpd2_status = 0x1c4,
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.rst_status = 0x1b4,
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.rst_source_shift = 0x0,
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.rst_source_mask = 0x7,
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.rst_level_shift = 0x0,
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.rst_level_mask = 0x0,
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};
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static void tegra20_pmc_init(struct tegra_pmc *pmc)
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@ -1719,6 +1817,10 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
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.regs = &tegra20_pmc_regs,
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.init = tegra20_pmc_init,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.reset_sources = NULL,
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.num_reset_sources = 0,
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.reset_levels = NULL,
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.num_reset_levels = 0,
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};
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static const char * const tegra30_powergates[] = {
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@ -1760,6 +1862,10 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
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.regs = &tegra20_pmc_regs,
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.init = tegra20_pmc_init,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.reset_sources = tegra30_reset_sources,
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.num_reset_sources = 5,
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.reset_levels = NULL,
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.num_reset_levels = 0,
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};
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static const char * const tegra114_powergates[] = {
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@ -1805,6 +1911,10 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
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.regs = &tegra20_pmc_regs,
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.init = tegra20_pmc_init,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.reset_sources = tegra30_reset_sources,
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.num_reset_sources = 5,
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.reset_levels = NULL,
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.num_reset_levels = 0,
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};
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static const char * const tegra124_powergates[] = {
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@ -1910,6 +2020,10 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
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.regs = &tegra20_pmc_regs,
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.init = tegra20_pmc_init,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.reset_sources = tegra30_reset_sources,
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.num_reset_sources = 5,
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.reset_levels = NULL,
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.num_reset_levels = 0,
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};
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static const char * const tegra210_powergates[] = {
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@ -2011,6 +2125,10 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
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.regs = &tegra20_pmc_regs,
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.init = tegra20_pmc_init,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.reset_sources = tegra30_reset_sources,
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.num_reset_sources = 5,
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.reset_levels = NULL,
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.num_reset_levels = 0,
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};
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#define TEGRA186_IO_PAD_TABLE(_pad) \
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@ -2068,6 +2186,11 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = {
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.dpd_status = 0x78,
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.dpd2_req = 0x7c,
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.dpd2_status = 0x80,
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.rst_status = 0x70,
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.rst_source_shift = 0x2,
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.rst_source_mask = 0x3C,
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.rst_level_shift = 0x0,
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.rst_level_mask = 0x3,
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};
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static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
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@ -2120,6 +2243,10 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
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.regs = &tegra186_pmc_regs,
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.init = NULL,
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.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
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.reset_sources = tegra186_reset_sources,
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.num_reset_sources = 14,
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.reset_levels = tegra186_reset_levels,
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.num_reset_levels = 3,
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};
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static const struct of_device_id tegra_pmc_match[] = {
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