KVM: arm/arm64: vgic: Handle GICR_PENDBASER.PTZ filed as RAZ
Although guest will hardly read and use the PTZ (Pending Table Zero) bit in GICR_PENDBASER, let us emulate the architecture strictly. As per IHI 0069E 9.11.30, PTZ field is WO, and reads as 0. Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Link: https://lore.kernel.org/r/20191220111833.1422-1-yuzenghui@huawei.com
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@ -414,8 +414,11 @@ static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
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u64 value = vgic_cpu->pendbaser;
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return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
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value &= ~GICR_PENDBASER_PTZ;
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return extract_bytes(value, addr & 7, len);
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}
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static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
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