UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

net: lan78xx: update for phy_(read|write)_mmd_indirect() removal 

lan78xx appears to use phylib in a rather weird way, accessing the PHY
partly through phylib, and partly by making direct accesses to it,
including to the Clause 45 registers.  As the indirect MMD accessors are
going away, update this driver to use the plain phy_(read|write)_mmd()
accessors instead.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Woojung Huh <Woojung.Huh@microchip.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King 2017-03-21 16:36:48 +00:00 committed by David S. Miller
parent 1ee6b9bc62
commit 5f61367729
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/net/usb/lan78xx.c
View File

@ -1952,10 +1952,10 @@ static int lan8835_fixup(struct phy_device *phydev)
struct lan78xx_net *dev = netdev_priv(phydev->attached_dev); struct lan78xx_net *dev = netdev_priv(phydev->attached_dev);
/* LED2/PME_N/IRQ_N/RGMII_ID pin to IRQ_N mode */ /* LED2/PME_N/IRQ_N/RGMII_ID pin to IRQ_N mode */
buf = phy_read_mmd_indirect(phydev, 0x8010, 3); buf = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8010);
buf &= ~0x1800; buf &= ~0x1800;
buf |= 0x0800; buf |= 0x0800;
phy_write_mmd_indirect(phydev, 0x8010, 3, buf); phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8010, buf);
/* RGMII MAC TXC Delay Enable */ /* RGMII MAC TXC Delay Enable */
ret = lan78xx_write_reg(dev, MAC_RGMII_ID, ret = lan78xx_write_reg(dev, MAC_RGMII_ID,
@ -1975,11 +1975,11 @@ static int ksz9031rnx_fixup(struct phy_device *phydev)
/* Micrel9301RNX PHY configuration */ /* Micrel9301RNX PHY configuration */
/* RGMII Control Signal Pad Skew */ /* RGMII Control Signal Pad Skew */
phy_write_mmd_indirect(phydev, 4, 2, 0x0077); phy_write_mmd(phydev, MDIO_MMD_WIS, 4, 0x0077);
/* RGMII RX Data Pad Skew */ /* RGMII RX Data Pad Skew */
phy_write_mmd_indirect(phydev, 5, 2, 0x7777); phy_write_mmd(phydev, MDIO_MMD_WIS, 5, 0x7777);
/* RGMII RX Clock Pad Skew */ /* RGMII RX Clock Pad Skew */
phy_write_mmd_indirect(phydev, 8, 2, 0x1FF); phy_write_mmd(phydev, MDIO_MMD_WIS, 8, 0x1FF);
dev->interface = PHY_INTERFACE_MODE_RGMII_RXID; dev->interface = PHY_INTERFACE_MODE_RGMII_RXID;