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arm64: dts: renesas: r8a774a1: Add CPU capacity-dmips-mhz 

Set the capacity-dmips-mhz for RZ/G2M(r8a774a1) SoC, that is based on
dhrystone.

Based on work done by Gaku Inami <gaku.inami.xw@bp.renesas.com> for
r8a7796 SoC.

The average dhrystone result for 5 iterations is as below:

r8a774a1 SoC (CA57x2 + CA53x4)
  CPU   max-freq   dhrystone
  ---------------------------------
  CA57   1500 MHz  11428571 lps/s
  CA53   1200 MHz   5000000 lps/s

From this, CPU capacity-dmips-mhz for CA57 and CA53 are calculated
as follows:

r8a774a1 SoC
  CA57 : 1024 / (11428571 / 1500) * (11428571 / 1500) = 1024
  CA53 : 1024 / (11428571 / 1500) * ( 5000000 / 1200) =  560

Since each CPUs have different max frequencies, the final CPU
capacities of A53 scaled by the above difference is as below

$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024
1024
448
448
448
448

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Biju Das 2019-06-12 15:20:53 +01:00 committed by Simon Horman
parent 7b996955e5
commit 5f5249497b
1 changed files with 6 additions and 0 deletions
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6
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
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@ -137,6 +137,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
};
a57_1: cpu@1 {
@ -148,6 +149,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
};
a53_0: cpu@100 {
@ -159,6 +161,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <560>;
};
a53_1: cpu@101 {
@ -170,6 +173,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <560>;
};
a53_2: cpu@102 {
@ -181,6 +185,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <560>;
};
a53_3: cpu@103 {
@ -192,6 +197,7 @@
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <560>;
};
L2_CA57: cache-controller-0 {