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PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() 

The "num-lanes" DT property is parsed in dw_pcie_host_init(). However
num-lanes is applicable to both root complex mode and endpoint mode. As a
first step, move the parsing of this property outside dw_pcie_host_init().
This is in preparation for splitting pcie-designware.c to pcie-designware.c
and pcie-designware-host.c

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Kishon Vijay Abraham I 2017-02-15 18:48:15 +05:30 committed by Bjorn Helgaas
parent 442ec4c04d
commit 5f334db665
2 changed files with 11 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/pci/dwc/pcie-designware.c
View File

@ -548,10 +548,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
} }
} }
ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
if (ret)
pci->lanes = 0;
ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport); ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
if (ret) if (ret)
pci->num_viewport = 2; pci->num_viewport = 2;
@ -748,13 +744,21 @@ static struct pci_ops dw_pcie_ops = {
void dw_pcie_setup_rc(struct pcie_port *pp) void dw_pcie_setup_rc(struct pcie_port *pp)
{ {
int ret;
u32 lanes;
u32 val; u32 val;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct device *dev = pci->dev;
struct device_node *np = dev->of_node;
ret = of_property_read_u32(np, "num-lanes", &lanes);
if (ret)
lanes = 0;
/* set the number of lanes */ /* set the number of lanes */
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
val &= ~PORT_LINK_MODE_MASK; val &= ~PORT_LINK_MODE_MASK;
switch (pci->lanes) { switch (lanes) {
case 1: case 1:
val |= PORT_LINK_MODE_1_LANES; val |= PORT_LINK_MODE_1_LANES;
break; break;
@ -768,7 +772,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
val |= PORT_LINK_MODE_8_LANES; val |= PORT_LINK_MODE_8_LANES;
break; break;
default: default:
dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->lanes); dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
return; return;
} }
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
@ -776,7 +780,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
/* set link width speed control register */ /* set link width speed control register */
val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
val &= ~PORT_LOGIC_LINK_WIDTH_MASK; val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
switch (pci->lanes) { switch (lanes) {
case 1: case 1:
val |= PORT_LOGIC_LINK_WIDTH_1_LANES; val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
break; break;

1
drivers/pci/dwc/pcie-designware.h
View File

@ -147,7 +147,6 @@ struct dw_pcie_ops {
struct dw_pcie { struct dw_pcie {
struct device *dev; struct device *dev;
void __iomem *dbi_base; void __iomem *dbi_base;
u32 lanes;
u32 num_viewport; u32 num_viewport;
u8 iatu_unroll_enabled; u8 iatu_unroll_enabled;
struct pcie_port pp; struct pcie_port pp;