crypto: cavium/nitrox - Configure asymmetric queue manager Hardware unit
This patch configures and initializes CNN55XX device AQM hardware unit. Signed-off-by: Phani Kiran Hemadri <phemadri@marvell.com> Reviewed-by: Srikanth Jampala <jsrikanth@marvell.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Phani Kiran Hemadri
Herbert Xu
parent
b31c17c852
commit
5f05cdca27
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@ -256,6 +256,117 @@ union aqm_grp_execmsk_hi {
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};
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};
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/**
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* struct aqmq_drbl - AQM Queue Doorbell Counter Registers
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* @dbell_count: Doorbell Counter
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*/
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union aqmq_drbl {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_32_63 : 32;
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u64 dbell_count : 32;
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#else
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u64 dbell_count : 32;
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u64 raz_32_63 : 32;
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#endif
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};
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};
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/**
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* struct aqmq_qsz - AQM Queue Host Queue Size Registers
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* @host_queue_size: Size, in numbers of 'aqmq_command_s' command
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* of the Host Ring.
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*/
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union aqmq_qsz {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_32_63 : 32;
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u64 host_queue_size : 32;
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#else
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u64 host_queue_size : 32;
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u64 raz_32_63 : 32;
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#endif
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};
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};
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/**
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* struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers
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* @commands_completed_threshold: Count of 'aqmq_command_s' commands executed
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* by AE engines for which completion interrupt is asserted.
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*/
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union aqmq_cmp_thr {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_32_63 : 32;
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u64 commands_completed_threshold : 32;
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#else
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u64 commands_completed_threshold : 32;
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u64 raz_32_63 : 32;
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#endif
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};
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};
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/**
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* struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers
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* @resend: Bit to request completion interrupt Resend.
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* @completion_status: Command completion status of the ring.
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* @commands_completed_count: Count of 'aqmq_command_s' commands executed by
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* AE engines.
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*/
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union aqmq_cmp_cnt {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_34_63 : 30;
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u64 resend : 1;
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u64 completion_status : 1;
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u64 commands_completed_count : 32;
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#else
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u64 commands_completed_count : 32;
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u64 completion_status : 1;
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u64 resend : 1;
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u64 raz_34_63 : 30;
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#endif
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};
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};
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/**
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* struct aqmq_en - AQM Queue Enable Registers
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* @queue_status: 1 = AQMQ is enabled, 0 = AQMQ is disabled
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*/
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union aqmq_en {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_1_63 : 63;
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u64 queue_enable : 1;
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#else
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u64 queue_enable : 1;
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u64 raz_1_63 : 63;
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#endif
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};
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};
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/**
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* struct aqmq_activity_stat - AQM Queue Activity Status Registers
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* @queue_active: 1 = AQMQ is active, 0 = AQMQ is quiescent
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*/
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union aqmq_activity_stat {
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u64 value;
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struct {
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#if (defined(__BIG_ENDIAN_BITFIELD))
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u64 raz_1_63 : 63;
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u64 queue_active : 1;
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#else
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u64 queue_active : 1;
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u64 raz_1_63 : 63;
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#endif
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};
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};
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/**
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* struct emu_fuse_map - EMU Fuse Map Registers
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* @ae_fuse: Fuse settings for AE 19..0
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@ -241,12 +241,12 @@ void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev)
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}
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/**
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* enable_nps_interrupts - enable NPS interrutps
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* enable_nps_core_interrupts - enable NPS core interrutps
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* @ndev: NITROX device.
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*
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* This includes NPS core, packet in and slc interrupts.
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* This includes NPS core interrupts.
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*/
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static void enable_nps_interrupts(struct nitrox_device *ndev)
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static void enable_nps_core_interrupts(struct nitrox_device *ndev)
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{
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union nps_core_int_ena_w1s core_int;
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@ -258,18 +258,9 @@ static void enable_nps_interrupts(struct nitrox_device *ndev)
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core_int.s.npco_dma_malform = 1;
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core_int.s.host_nps_wr_err = 1;
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nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);
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/* NPS packet in ring interrupts */
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nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL));
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/* NPS packet slc port interrupts */
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nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL));
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}
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void nitrox_config_nps_unit(struct nitrox_device *ndev)
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void nitrox_config_nps_core_unit(struct nitrox_device *ndev)
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{
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union nps_core_gbl_vfcfg core_gbl_vfcfg;
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@ -281,12 +272,149 @@ void nitrox_config_nps_unit(struct nitrox_device *ndev)
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core_gbl_vfcfg.s.ilk_disable = 1;
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core_gbl_vfcfg.s.cfg = __NDEV_MODE_PF;
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nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);
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/* enable nps core interrupts */
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enable_nps_core_interrupts(ndev);
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}
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/**
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* enable_nps_pkt_interrupts - enable NPS packet interrutps
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* @ndev: NITROX device.
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*
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* This includes NPS packet in and slc interrupts.
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*/
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static void enable_nps_pkt_interrupts(struct nitrox_device *ndev)
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{
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/* NPS packet in ring interrupts */
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nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL));
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/* NPS packet slc port interrupts */
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nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL));
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}
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void nitrox_config_nps_pkt_unit(struct nitrox_device *ndev)
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{
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/* config input and solicit ports */
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nitrox_config_pkt_input_rings(ndev);
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nitrox_config_pkt_solicit_ports(ndev);
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/* enable interrupts */
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enable_nps_interrupts(ndev);
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/* enable nps packet interrupts */
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enable_nps_pkt_interrupts(ndev);
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}
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static void reset_aqm_ring(struct nitrox_device *ndev, int ring)
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{
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union aqmq_en aqmq_en_reg;
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union aqmq_activity_stat activity_stat;
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union aqmq_cmp_cnt cmp_cnt;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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/* step 1: disable the queue */
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offset = AQMQ_ENX(ring);
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aqmq_en_reg.value = 0;
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aqmq_en_reg.queue_enable = 0;
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nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
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/* step 2: wait for AQMQ_ACTIVITY_STATX[QUEUE_ACTIVE] to clear */
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usleep_range(100, 150);
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offset = AQMQ_ACTIVITY_STATX(ring);
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do {
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activity_stat.value = nitrox_read_csr(ndev, offset);
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if (!activity_stat.queue_active)
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break;
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udelay(50);
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} while (max_retries--);
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/* step 3: clear commands completed count */
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offset = AQMQ_CMP_CNTX(ring);
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cmp_cnt.value = nitrox_read_csr(ndev, offset);
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nitrox_write_csr(ndev, offset, cmp_cnt.value);
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usleep_range(50, 100);
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}
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void enable_aqm_ring(struct nitrox_device *ndev, int ring)
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{
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union aqmq_en aqmq_en_reg;
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u64 offset;
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offset = AQMQ_ENX(ring);
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aqmq_en_reg.value = 0;
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aqmq_en_reg.queue_enable = 1;
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nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
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usleep_range(50, 100);
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}
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void nitrox_config_aqm_rings(struct nitrox_device *ndev)
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{
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int ring;
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for (ring = 0; ring < ndev->nr_queues; ring++) {
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struct nitrox_cmdq *cmdq = ndev->aqmq[ring];
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union aqmq_drbl drbl;
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union aqmq_qsz qsize;
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union aqmq_cmp_thr cmp_thr;
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u64 offset;
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/* steps 1 - 3 */
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reset_aqm_ring(ndev, ring);
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/* step 4: clear doorbell count of ring */
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offset = AQMQ_DRBLX(ring);
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drbl.value = 0;
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drbl.dbell_count = 0xFFFFFFFF;
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nitrox_write_csr(ndev, offset, drbl.value);
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/* step 5: configure host ring details */
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/* set host address for next command of ring */
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offset = AQMQ_NXT_CMDX(ring);
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nitrox_write_csr(ndev, offset, 0ULL);
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/* set host address of ring base */
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offset = AQMQ_BADRX(ring);
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nitrox_write_csr(ndev, offset, cmdq->dma);
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/* set ring size */
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offset = AQMQ_QSZX(ring);
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qsize.value = 0;
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qsize.host_queue_size = ndev->qlen;
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nitrox_write_csr(ndev, offset, qsize.value);
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/* set command completion threshold */
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offset = AQMQ_CMP_THRX(ring);
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cmp_thr.value = 0;
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cmp_thr.commands_completed_threshold = 1;
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nitrox_write_csr(ndev, offset, cmp_thr.value);
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/* step 6: enable the queue */
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enable_aqm_ring(ndev, ring);
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}
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}
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static void enable_aqm_interrupts(struct nitrox_device *ndev)
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{
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/* clear interrupt enable bits */
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nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL));
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nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL));
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}
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void nitrox_config_aqm_unit(struct nitrox_device *ndev)
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{
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/* config aqm command queues */
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nitrox_config_aqm_rings(ndev);
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/* enable aqm interrupts */
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enable_aqm_interrupts(ndev);
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}
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void nitrox_config_pom_unit(struct nitrox_device *ndev)
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@ -4,10 +4,13 @@
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#include "nitrox_dev.h"
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void nitrox_config_aqm_rings(struct nitrox_device *ndev);
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void nitrox_config_aqm_unit(struct nitrox_device *ndev);
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void nitrox_config_emu_unit(struct nitrox_device *ndev);
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void nitrox_config_pkt_input_rings(struct nitrox_device *ndev);
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void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev);
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void nitrox_config_nps_unit(struct nitrox_device *ndev);
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void nitrox_config_nps_core_unit(struct nitrox_device *ndev);
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void nitrox_config_nps_pkt_unit(struct nitrox_device *ndev);
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void nitrox_config_pom_unit(struct nitrox_device *ndev);
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void nitrox_config_rand_unit(struct nitrox_device *ndev);
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void nitrox_config_efl_unit(struct nitrox_device *ndev);
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@ -15,6 +18,7 @@ void nitrox_config_bmi_unit(struct nitrox_device *ndev);
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void nitrox_config_bmo_unit(struct nitrox_device *ndev);
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void nitrox_config_lbc_unit(struct nitrox_device *ndev);
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void invalidate_lbc(struct nitrox_device *ndev);
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void enable_aqm_ring(struct nitrox_device *ndev, int qno);
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void enable_pkt_input_ring(struct nitrox_device *ndev, int ring);
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void enable_pkt_solicit_port(struct nitrox_device *ndev, int port);
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void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode);
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@ -387,7 +387,9 @@ static int nitrox_pf_hw_init(struct nitrox_device *ndev)
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/* get cores information */
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nitrox_get_hwinfo(ndev);
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nitrox_config_nps_unit(ndev);
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nitrox_config_nps_core_unit(ndev);
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nitrox_config_aqm_unit(ndev);
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nitrox_config_nps_pkt_unit(ndev);
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nitrox_config_pom_unit(ndev);
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nitrox_config_efl_unit(ndev);
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/* configure IO units */
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@ -109,6 +109,9 @@ static int nitrox_pf_reinit(struct nitrox_device *ndev)
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return err;
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}
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/* configure the AQM queues */
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nitrox_config_aqm_rings(ndev);
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/* configure the packet queues */
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nitrox_config_pkt_input_rings(ndev);
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nitrox_config_pkt_solicit_ports(ndev);
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