drm/amdgpu: add perfmons accessible during df c-states
During DF C-State, Perfmon counters outside of range 1D700-1D7FF will encounter SLVERR affecting xGMI performance monitoring. PerfmonCtr[7:4] is being added to avoid SLVERR during read since it falls within this range. PerfmonCtl[7:4] is being added in order to arm PerfmonCtr[7:4]. Since PerfmonCtl[7:4] exists outside of range 1D700-1D7FF, DF routines will be enabled to opportunistically re-arm PerfmonCtl[7:4] on retry after SLVERR. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Acked-by: Alex Deucher <Alexander.Deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -38,6 +38,14 @@
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#define smnPerfMonCtlHi2 0x01d464UL
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#define smnPerfMonCtlLo3 0x01d470UL
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#define smnPerfMonCtlHi3 0x01d474UL
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#define smnPerfMonCtlLo4 0x01d880UL
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#define smnPerfMonCtlHi4 0x01d884UL
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#define smnPerfMonCtlLo5 0x01d888UL
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#define smnPerfMonCtlHi5 0x01d88cUL
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#define smnPerfMonCtlLo6 0x01d890UL
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#define smnPerfMonCtlHi6 0x01d894UL
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#define smnPerfMonCtlLo7 0x01d898UL
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#define smnPerfMonCtlHi7 0x01d89cUL
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#define smnPerfMonCtrLo0 0x01d448UL
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#define smnPerfMonCtrHi0 0x01d44cUL
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@ -47,6 +55,14 @@
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#define smnPerfMonCtrHi2 0x01d46cUL
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#define smnPerfMonCtrLo3 0x01d478UL
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#define smnPerfMonCtrHi3 0x01d47cUL
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#define smnPerfMonCtrLo4 0x01d790UL
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#define smnPerfMonCtrHi4 0x01d794UL
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#define smnPerfMonCtrLo5 0x01d798UL
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#define smnPerfMonCtrHi5 0x01d79cUL
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#define smnPerfMonCtrLo6 0x01d7a0UL
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#define smnPerfMonCtrHi6 0x01d7a4UL
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#define smnPerfMonCtrLo7 0x01d7a8UL
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#define smnPerfMonCtrHi7 0x01d7acUL
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#define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3 0x1d05cUL
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#define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3 0x1d098UL
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