drm/i915/gvt: Fix guest boot warning
Simulate MIA core in reset status once GUC engine is reset. v2: 1. use vgpu_vreg_t() function, 2. clear MIA_IN_RESET after reading. (Zhenyu) v3: add comments. (Zhenyu) Signed-off-by: Gao Fred <fred.gao@intel.com> Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20191216160255.29499-1-fred.gao@intel.com
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@ -341,6 +341,10 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
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engine_mask |= BIT(VCS1);
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}
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if (data & GEN9_GRDOM_GUC) {
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gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
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vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
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}
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engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;
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}
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@ -1636,6 +1640,16 @@ static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
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return 0;
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}
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static int guc_status_read(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data,
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unsigned int bytes)
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{
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/* keep MIA_IN_RESET before clearing */
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read_vreg(vgpu, offset, p_data, bytes);
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vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
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return 0;
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}
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static int mmio_read_from_hw(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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@ -2672,6 +2686,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
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MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
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MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
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return 0;
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}
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