drm/amdgpu/gfx9: Raven has two MECs
This was missed when Andres' queue patches were rebased.
Fixes: 42794b27
(drm/amdgpu: take ownership of per-pipe configuration v3)
Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -872,6 +872,7 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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case CHIP_RAVEN:
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adev->gfx.mec.num_mec = 2;
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break;
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default:
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