drm/msm/adreno: Add Adreno A690 support
Introduce support for the Adreno A690, found in Qualcomm SC8280XP. Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/540335/ Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Bjorn Andersson
Rob Clark
parent
171f580e32
commit
5e7665b5e4
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@ -588,6 +588,63 @@ const struct adreno_reglist a660_hwcg[] = {
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{},
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};
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const struct adreno_reglist a690_hwcg[] = {
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{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
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{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
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{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
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{REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
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{REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
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{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
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{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
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{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
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{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
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{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
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{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
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{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
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{REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
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{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
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{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
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{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
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{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
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{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
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{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
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{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
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{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
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{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
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{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
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{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
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{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
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{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
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{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
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{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
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{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
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{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
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{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
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{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
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{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
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{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
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{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
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{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
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{REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
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{REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
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{REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
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{REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
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{REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
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{REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
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{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
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{REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
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{REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
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{REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
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{REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
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{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
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{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
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{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
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{REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
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{REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
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{REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
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{}
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};
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static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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@ -747,6 +804,45 @@ static const u32 a660_protect[] = {
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A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
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};
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/* These are for a690 */
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static const u32 a690_protect[] = {
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A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
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A6XX_PROTECT_RDONLY(0x00501, 0x00001),
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A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
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A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
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A6XX_PROTECT_NORDWR(0x00510, 0x00000),
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A6XX_PROTECT_NORDWR(0x00534, 0x00000),
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A6XX_PROTECT_NORDWR(0x00800, 0x00082),
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A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
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A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
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A6XX_PROTECT_RDONLY(0x008d0, 0x000bc),
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A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
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A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
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A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
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A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
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A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
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A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
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A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
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A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
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A6XX_PROTECT_NORDWR(0x08e08, 0x00008),
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A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
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A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
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A6XX_PROTECT_NORDWR(0x09624, 0x001db),
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A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
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A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
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A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
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A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
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A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
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A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
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A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
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A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
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A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
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A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
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A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
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A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
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A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
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};
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static void a6xx_set_cp_protect(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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@ -758,6 +854,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
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count = ARRAY_SIZE(a650_protect);
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count_max = 48;
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BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
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} else if (adreno_is_a690(adreno_gpu)) {
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regs = a690_protect;
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count = ARRAY_SIZE(a690_protect);
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count_max = 48;
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BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);
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} else if (adreno_is_a660_family(adreno_gpu)) {
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regs = a660_protect;
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count = ARRAY_SIZE(a660_protect);
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@ -806,6 +907,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
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uavflagprd_inv = 2;
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}
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if (adreno_is_a690(adreno_gpu)) {
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lower_bit = 2;
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amsbc = 1;
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rgb565_predicator = 1;
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uavflagprd_inv = 2;
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}
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if (adreno_is_7c3(adreno_gpu)) {
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lower_bit = 1;
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amsbc = 1;
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@ -1084,7 +1192,7 @@ static int hw_init(struct msm_gpu *gpu)
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/* Setting the primFifo thresholds default values,
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* and vccCacheSkipDis=1 bit (0x200) for A640 and newer
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*/
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if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
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if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu))
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gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
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else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
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gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
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@ -1994,7 +2102,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
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info = adreno_info(config->rev);
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if (info && (info->revn == 650 || info->revn == 660 ||
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adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
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info->revn == 690 ||
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adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
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adreno_gpu->base.hw_apriv = true;
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a6xx_llc_slices_init(pdev, a6xx_gpu);
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@ -414,6 +414,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
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msg->cnoc_cmds_data[1][0] = 0x60000001;
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}
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static void a690_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
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{
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/*
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* Send a single "off" entry just to get things running
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* TODO: bus scaling
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*/
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msg->bw_level_num = 1;
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msg->ddr_cmds_num = 3;
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msg->ddr_wait_bitmask = 0x01;
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msg->ddr_cmds_addrs[0] = 0x50004;
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msg->ddr_cmds_addrs[1] = 0x50000;
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msg->ddr_cmds_addrs[2] = 0x500ac;
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msg->ddr_cmds_data[0][0] = 0x40000000;
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msg->ddr_cmds_data[0][1] = 0x40000000;
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msg->ddr_cmds_data[0][2] = 0x40000000;
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/*
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* These are the CX (CNOC) votes - these are used by the GMU but the
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* votes are known and fixed for the target
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*/
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msg->cnoc_cmds_num = 1;
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msg->cnoc_wait_bitmask = 0x01;
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msg->cnoc_cmds_addrs[0] = 0x5003c;
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msg->cnoc_cmds_data[0][0] = 0x40000000;
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msg->cnoc_cmds_data[1][0] = 0x60000001;
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}
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static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
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{
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/*
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@ -531,6 +562,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
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adreno_7c3_build_bw_table(&msg);
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else if (adreno_is_a660(adreno_gpu))
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a660_build_bw_table(&msg);
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else if (adreno_is_a690(adreno_gpu))
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a690_build_bw_table(&msg);
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else
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a6xx_build_bw_table(&msg);
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@ -355,6 +355,20 @@ static const struct adreno_info gpulist[] = {
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.init = a6xx_gpu_init,
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.zapfw = "a640_zap.mdt",
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.hwcg = a640_hwcg,
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}, {
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.rev = ADRENO_REV(6, 9, 0, ANY_ID),
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.revn = 690,
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.name = "A690",
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.fw = {
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[ADRENO_FW_SQE] = "a660_sqe.fw",
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[ADRENO_FW_GMU] = "a690_gmu.bin",
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},
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.gmem = SZ_4M,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a6xx_gpu_init,
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.zapfw = "a690_zap.mdt",
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.hwcg = a690_hwcg,
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.address_space_size = SZ_16G,
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},
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};
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@ -55,7 +55,7 @@ struct adreno_reglist {
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u32 value;
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};
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extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
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extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
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struct adreno_info {
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struct adreno_rev rev;
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@ -272,6 +272,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu)
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return gpu->revn == 660;
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}
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static inline int adreno_is_a690(struct adreno_gpu *gpu)
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{
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return gpu->revn == 690;
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};
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/* check for a615, a616, a618, a619 or any derivatives */
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static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
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{
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@ -280,13 +285,13 @@ static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
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static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
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{
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return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
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return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
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}
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/* check for a650, a660, or any derivatives */
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static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
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{
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return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
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return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
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}
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u64 adreno_private_address_space_size(struct msm_gpu *gpu);
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