drm/amdgpu: add support for IP discovery gc_info table v2
Used on gfx9 based systems. Fixes incorrect CU counts reported in the kernel log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -526,10 +526,15 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
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}
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}
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union gc_info {
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struct gc_info_v1_0 v1;
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struct gc_info_v2_0 v2;
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};
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int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
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{
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struct binary_header *bhdr;
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struct gc_info_v1_0 *gc_info;
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union gc_info *gc_info;
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if (!adev->mman.discovery_bin) {
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DRM_ERROR("ip discovery uninitialized\n");
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@ -537,28 +542,55 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
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}
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bhdr = (struct binary_header *)adev->mman.discovery_bin;
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gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +
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gc_info = (union gc_info *)(adev->mman.discovery_bin +
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le16_to_cpu(bhdr->table_list[GC].offset));
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adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
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adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
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le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
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adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
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adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
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adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
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adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
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adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
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adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
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adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
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adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
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adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
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adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
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adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
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adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
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adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
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le32_to_cpu(gc_info->gc_num_sa_per_se);
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adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
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switch (gc_info->v1.header.version_major) {
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case 1:
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adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
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adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
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le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
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adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
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adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
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adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
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adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
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adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
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adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
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adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
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adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
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adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
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adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
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adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
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adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
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adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
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le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
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adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
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break;
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case 2:
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adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
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adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
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adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
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adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
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adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
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adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
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adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
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adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
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adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
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adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
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adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
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adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
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adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
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adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
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adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
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le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
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adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
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break;
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default:
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dev_err(adev->dev,
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"Unhandled GC info table %d.%d\n",
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gc_info->v1.header.version_major,
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gc_info->v1.header.version_minor);
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return -EINVAL;
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}
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return 0;
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}
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@ -143,6 +143,55 @@ struct gc_info_v1_0 {
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uint32_t gc_num_gl2a;
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};
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struct gc_info_v1_1 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_wgp0_per_sa;
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uint32_t gc_num_wgp1_per_sa;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_gl2c;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_sa_per_se;
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uint32_t gc_num_packer_per_sc;
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uint32_t gc_num_gl2a;
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uint32_t gc_num_tcp_per_sa;
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uint32_t gc_num_sdp_interface;
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uint32_t gc_num_tcps;
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};
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struct gc_info_v2_0 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_cu_per_sh;
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uint32_t gc_num_sh_per_se;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_tccs;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_packer_per_sc;
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};
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typedef struct harvest_info_header {
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uint32_t signature; /* Table Signature */
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uint32_t version; /* Table Version */
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