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drm/amd/display: remove dead code 

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tony Cheng 2017-01-14 20:56:08 -05:00 committed by Alex Deucher
parent a10eadfb15
commit 5e701406ed
5 changed files with 0 additions and 223 deletions
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76
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
View File

@ -545,80 +545,6 @@ static enum bp_result bios_parser_get_hpd_info(struct dc_bios *dcb,
return BP_RESULT_NORECORD;
}
static uint32_t bios_parser_get_gpio_record(
struct dc_bios *dcb,
struct graphics_object_id id,
struct bp_gpio_cntl_info *gpio_record,
uint32_t record_size)
{
struct bios_parser *bp = BP_FROM_DCB(dcb);
ATOM_COMMON_RECORD_HEADER *header = NULL;
ATOM_OBJECT_GPIO_CNTL_RECORD *record = NULL;
ATOM_OBJECT *object = get_bios_object(bp, id);
uint32_t offset;
uint32_t pins_number;
uint32_t i;
if (!object)
return 0;
/* Initialise offset */
offset = le16_to_cpu(object->usRecordOffset)
+ bp->object_info_tbl_offset;
for (;;) {
/* Get record header */
header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
if (!header || header->ucRecordType == LAST_RECORD_TYPE ||
!header->ucRecordSize)
break;
/* If this is gpio control record - stop. We found the record */
if (header->ucRecordType == ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE
&& header->ucRecordSize
>= sizeof(ATOM_OBJECT_GPIO_CNTL_RECORD)) {
record = (ATOM_OBJECT_GPIO_CNTL_RECORD *) header;
break;
}
/* Advance to next record */
offset += header->ucRecordSize;
}
/* If we did not find a record - return */
if (!record)
return 0;
/* Extract gpio IDs from bios record (make sure we do not exceed passed
* array size) */
pins_number = (record->ucNumberOfPins < record_size ?
record->ucNumberOfPins : record_size);
for (i = 0; i < pins_number; i++) {
uint8_t output_state = ((record->asGpio[i].ucGPIO_PinState
& GPIO_PIN_OUTPUT_STATE_MASK)
>> GPIO_PIN_OUTPUT_STATE_SHIFT);
gpio_record[i].id = record->asGpio[i].ucGPIOID;
switch (output_state) {
case GPIO_PIN_STATE_ACTIVE_LOW:
gpio_record[i].state =
GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW;
break;
case GPIO_PIN_STATE_ACTIVE_HIGH:
gpio_record[i].state =
GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH;
break;
default:
BREAK_TO_DEBUGGER(); /* Invalid Pin Output State */
break;
}
}
return pins_number;
}
enum bp_result bios_parser_get_device_tag_record(
struct bios_parser *bp,
ATOM_OBJECT *object,
@ -4064,8 +3990,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
.get_dst_number = bios_parser_get_dst_number,
.get_gpio_record = bios_parser_get_gpio_record,
.get_src_obj = bios_parser_get_src_obj,
.get_dst_obj = bios_parser_get_dst_obj,

114
drivers/gpu/drm/amd/display/dc/bios/command_table.c
View File

@ -54,12 +54,10 @@ static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp);
static void init_adjust_display_pll(struct bios_parser *bp);
static void init_dac_encoder_control(struct bios_parser *bp);
static void init_dac_output_control(struct bios_parser *bp);
static void init_blank_crtc(struct bios_parser *bp);
static void init_set_crtc_timing(struct bios_parser *bp);
static void init_select_crtc_source(struct bios_parser *bp);
static void init_enable_crtc(struct bios_parser *bp);
static void init_enable_crtc_mem_req(struct bios_parser *bp);
static void init_compute_memore_engine_pll(struct bios_parser *bp);
static void init_external_encoder_control(struct bios_parser *bp);
static void init_enable_disp_power_gating(struct bios_parser *bp);
static void init_program_clock(struct bios_parser *bp);
@ -74,13 +72,11 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
init_adjust_display_pll(bp);
init_dac_encoder_control(bp);
init_dac_output_control(bp);
init_blank_crtc(bp);
init_set_crtc_timing(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp);
init_enable_crtc_mem_req(bp);
init_program_clock(bp);
init_compute_memore_engine_pll(bp);
init_external_encoder_control(bp);
init_enable_disp_power_gating(bp);
init_set_dce_clock(bp);
@ -1673,66 +1669,6 @@ static enum bp_result dac2_output_control_v1(
return result;
}
/*******************************************************************************
********************************************************************************
**
** BLANK CRTC
**
********************************************************************************
*******************************************************************************/
static enum bp_result blank_crtc_v1(
struct bios_parser *bp,
struct bp_blank_crtc_parameters *bp_params,
bool blank);
static void init_blank_crtc(struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(BlankCRTC)) {
case 1:
bp->cmd_tbl.blank_crtc = blank_crtc_v1;
break;
default:
bp->cmd_tbl.blank_crtc = NULL;
break;
}
}
static enum bp_result blank_crtc_v1(
struct bios_parser *bp,
struct bp_blank_crtc_parameters *bp_params,
bool blank)
{
enum bp_result result = BP_RESULT_FAILURE;
BLANK_CRTC_PARAMETERS params = {0};
uint8_t atom_controller_id;
if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
&atom_controller_id)) {
params.ucCRTC = (uint8_t)atom_controller_id;
if (blank)
params.ucBlanking = ATOM_BLANKING;
else
params.ucBlanking = ATOM_BLANKING_OFF;
params.usBlackColorRCr =
cpu_to_le16((uint16_t)bp_params->black_color_rcr);
params.usBlackColorGY =
cpu_to_le16((uint16_t)bp_params->black_color_gy);
params.usBlackColorBCb =
cpu_to_le16((uint16_t)bp_params->black_color_bcb);
if (EXEC_BIOS_CMD_TABLE(BlankCRTC, params))
result = BP_RESULT_OK;
} else
/* Not support more than two CRTC as current ASIC, update this
* if needed.
*/
result = BP_RESULT_BADINPUT;
return result;
}
/*******************************************************************************
********************************************************************************
**
@ -2239,56 +2175,6 @@ static enum bp_result program_clock_v6(
return result;
}
/*******************************************************************************
********************************************************************************
**
** COMPUTE MEMORY ENGINE PLL
**
********************************************************************************
*******************************************************************************/
static enum bp_result compute_memore_engine_pll_v4(
struct bios_parser *bp,
struct bp_display_clock_parameters *bp_params);
static void init_compute_memore_engine_pll(struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(ComputeMemoryEnginePLL)) {
case 4:
bp->cmd_tbl.compute_memore_engine_pll =
compute_memore_engine_pll_v4;
break;
default:
bp->cmd_tbl.compute_memore_engine_pll = NULL;
break;
}
}
static enum bp_result compute_memore_engine_pll_v4(
struct bios_parser *bp,
struct bp_display_clock_parameters *bp_params)
{
enum bp_result result = BP_RESULT_FAILURE;
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 params;
memset(&params, 0, sizeof(params));
params.ulClock = cpu_to_le32(bp_params->target_display_clock / 10);
/* Initialize this to the target clock in case this call fails */
bp_params->actual_display_clock = bp_params->target_display_clock;
if (EXEC_BIOS_CMD_TABLE(ComputeMemoryEnginePLL, params)) {
/* Convert from 10KHz units back to KHz */
bp_params->actual_display_clock =
le32_to_cpu(params.ulClock) * 10;
bp_params->actual_post_divider_id = params.ucPostDiv;
result = BP_RESULT_OK;
}
return result;
}
/*******************************************************************************
********************************************************************************
**

7
drivers/gpu/drm/amd/display/dc/bios/command_table.h
View File

@ -68,10 +68,6 @@ struct cmd_tbl {
enum bp_result (*dac2_output_control)(
struct bios_parser *bp,
bool enable);
enum bp_result (*blank_crtc)(
struct bios_parser *bp,
struct bp_blank_crtc_parameters *bp_params,
bool blank);
enum bp_result (*set_crtc_timing)(
struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params);
@ -89,9 +85,6 @@ struct cmd_tbl {
enum bp_result (*program_clock)(
struct bios_parser *bp,
struct bp_pixel_clock_parameters *bp_params);
enum bp_result (*compute_memore_engine_pll)(
struct bios_parser *bp,
struct bp_display_clock_parameters *bp_params);
enum bp_result (*external_encoder_control)(
struct bios_parser *bp,
struct bp_external_encoder_control *cntl);

6
drivers/gpu/drm/amd/display/dc/dc_bios_types.h
View File

@ -51,12 +51,6 @@ struct dc_vbios_funcs {
struct dc_bios *bios,
struct graphics_object_id id);
uint32_t (*get_gpio_record)(
struct dc_bios *dcb,
struct graphics_object_id id,
struct bp_gpio_cntl_info *gpio_record,
uint32_t record_size);
enum bp_result (*get_src_obj)(
struct dc_bios *bios,
struct graphics_object_id object_id, uint32_t index,

20
drivers/gpu/drm/amd/display/include/bios_parser_types.h
View File

@ -156,13 +156,6 @@ struct bp_transmitter_control {
bool single_pll_mode;
};
struct bp_blank_crtc_parameters {
enum controller_id controller_id;
uint32_t black_color_rcr;
uint32_t black_color_gy;
uint32_t black_color_bcb;
};
struct bp_hw_crtc_timing_parameters {
enum controller_id controller_id;
/* horizontal part */
@ -252,14 +245,6 @@ struct bp_pixel_clock_parameters {
} flags;
};
struct bp_display_clock_parameters {
uint32_t target_display_clock; /* KHz */
/* Actual Display Clock set due to clock divider granularity KHz */
uint32_t actual_display_clock;
/* Actual Post Divider ID used to generate the actual clock */
uint32_t actual_post_divider_id;
};
enum bp_dce_clock_type {
DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
DCECLOCK_TYPE_DPREFCLK = 1
@ -322,9 +307,4 @@ struct bp_encoder_cap_info {
uint32_t RESERVED:30;
};
struct bp_gpio_cntl_info {
uint32_t id;
enum gpio_pin_output_state state;
};
#endif /*__DAL_BIOS_PARSER_TYPES_H__ */