usb: gadget: mv_udc: drop ARCH dependency
This patch do the following things: 1. Change the Kconfig information. 2. Rename the driver name. 3. Don't do any type cast to io memory. 4. Add dummy stub for clk framework. Signed-off-by: Neil Zhang <zhangwm@marvell.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
parent
c2bbd16b03
commit
5e6c86b017
|
@ -309,13 +309,13 @@ config USB_S3C_HSUDC
|
||||||
|
|
||||||
This driver has been tested on S3C2416 and S3C2450 processors.
|
This driver has been tested on S3C2416 and S3C2450 processors.
|
||||||
|
|
||||||
config USB_PXA_U2O
|
config USB_MV_UDC
|
||||||
tristate "PXA9xx Processor USB2.0 controller"
|
tristate "Marvell USB2.0 Device Controller"
|
||||||
depends on ARCH_MMP
|
|
||||||
select USB_GADGET_DUALSPEED
|
select USB_GADGET_DUALSPEED
|
||||||
help
|
help
|
||||||
PXA9xx Processor series include a high speed USB2.0 device
|
Marvell Socs (including PXA and MMP series) include a high speed
|
||||||
controller, which support high speed and full speed USB peripheral.
|
USB2.0 OTG controller, which can be configured as high speed or
|
||||||
|
full speed USB peripheral.
|
||||||
|
|
||||||
config USB_GADGET_DWC3
|
config USB_GADGET_DWC3
|
||||||
tristate "DesignWare USB3.0 (DRD) Controller"
|
tristate "DesignWare USB3.0 (DRD) Controller"
|
||||||
|
|
|
@ -27,7 +27,7 @@ obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
|
||||||
obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
|
obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
|
||||||
obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
|
obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
|
||||||
obj-$(CONFIG_USB_EG20T) += pch_udc.o
|
obj-$(CONFIG_USB_EG20T) += pch_udc.o
|
||||||
obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
|
obj-$(CONFIG_USB_MV_UDC) += mv_udc.o
|
||||||
mv_udc-y := mv_udc_core.o
|
mv_udc-y := mv_udc_core.o
|
||||||
obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o
|
obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o
|
||||||
obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
|
obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
|
||||||
|
|
|
@ -180,7 +180,7 @@ struct mv_udc {
|
||||||
|
|
||||||
struct mv_cap_regs __iomem *cap_regs;
|
struct mv_cap_regs __iomem *cap_regs;
|
||||||
struct mv_op_regs __iomem *op_regs;
|
struct mv_op_regs __iomem *op_regs;
|
||||||
unsigned int phy_regs;
|
void __iomem *phy_regs;
|
||||||
unsigned int max_eps;
|
unsigned int max_eps;
|
||||||
struct mv_dqh *ep_dqh;
|
struct mv_dqh *ep_dqh;
|
||||||
size_t ep_dqh_size;
|
size_t ep_dqh_size;
|
||||||
|
|
|
@ -2128,11 +2128,9 @@ static int __devexit mv_udc_remove(struct platform_device *dev)
|
||||||
|
|
||||||
if (udc->cap_regs)
|
if (udc->cap_regs)
|
||||||
iounmap(udc->cap_regs);
|
iounmap(udc->cap_regs);
|
||||||
udc->cap_regs = NULL;
|
|
||||||
|
|
||||||
if (udc->phy_regs)
|
if (udc->phy_regs)
|
||||||
iounmap((void *)udc->phy_regs);
|
iounmap(udc->phy_regs);
|
||||||
udc->phy_regs = 0;
|
|
||||||
|
|
||||||
if (udc->status_req) {
|
if (udc->status_req) {
|
||||||
kfree(udc->status_req->req.buf);
|
kfree(udc->status_req->req.buf);
|
||||||
|
@ -2217,8 +2215,8 @@ static int __devinit mv_udc_probe(struct platform_device *dev)
|
||||||
goto err_iounmap_capreg;
|
goto err_iounmap_capreg;
|
||||||
}
|
}
|
||||||
|
|
||||||
udc->phy_regs = (unsigned int)ioremap(r->start, resource_size(r));
|
udc->phy_regs = ioremap(r->start, resource_size(r));
|
||||||
if (udc->phy_regs == 0) {
|
if (udc->phy_regs == NULL) {
|
||||||
dev_err(&dev->dev, "failed to map phy I/O memory\n");
|
dev_err(&dev->dev, "failed to map phy I/O memory\n");
|
||||||
retval = -EBUSY;
|
retval = -EBUSY;
|
||||||
goto err_iounmap_capreg;
|
goto err_iounmap_capreg;
|
||||||
|
@ -2229,7 +2227,8 @@ static int __devinit mv_udc_probe(struct platform_device *dev)
|
||||||
if (retval)
|
if (retval)
|
||||||
goto err_iounmap_phyreg;
|
goto err_iounmap_phyreg;
|
||||||
|
|
||||||
udc->op_regs = (struct mv_op_regs __iomem *)((u32)udc->cap_regs
|
udc->op_regs =
|
||||||
|
(struct mv_op_regs __iomem *)((unsigned long)udc->cap_regs
|
||||||
+ (readl(&udc->cap_regs->caplength_hciversion)
|
+ (readl(&udc->cap_regs->caplength_hciversion)
|
||||||
& CAPLENGTH_MASK));
|
& CAPLENGTH_MASK));
|
||||||
udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
|
udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
|
||||||
|
@ -2389,7 +2388,7 @@ err_free_dma:
|
||||||
err_disable_clock:
|
err_disable_clock:
|
||||||
mv_udc_disable_internal(udc);
|
mv_udc_disable_internal(udc);
|
||||||
err_iounmap_phyreg:
|
err_iounmap_phyreg:
|
||||||
iounmap((void *)udc->phy_regs);
|
iounmap(udc->phy_regs);
|
||||||
err_iounmap_capreg:
|
err_iounmap_capreg:
|
||||||
iounmap(udc->cap_regs);
|
iounmap(udc->cap_regs);
|
||||||
err_put_clk:
|
err_put_clk:
|
||||||
|
@ -2480,13 +2479,13 @@ static struct platform_driver udc_driver = {
|
||||||
.shutdown = mv_udc_shutdown,
|
.shutdown = mv_udc_shutdown,
|
||||||
.driver = {
|
.driver = {
|
||||||
.owner = THIS_MODULE,
|
.owner = THIS_MODULE,
|
||||||
.name = "pxa-u2o",
|
.name = "mv-udc",
|
||||||
#ifdef CONFIG_PM
|
#ifdef CONFIG_PM
|
||||||
.pm = &mv_udc_pm_ops,
|
.pm = &mv_udc_pm_ops,
|
||||||
#endif
|
#endif
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
MODULE_ALIAS("platform:pxa-u2o");
|
MODULE_ALIAS("platform:mv-udc");
|
||||||
|
|
||||||
MODULE_DESCRIPTION(DRIVER_DESC);
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
||||||
MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
|
MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
|
||||||
|
|
|
@ -42,9 +42,17 @@ struct mv_usb_platform_data {
|
||||||
/* only valid for HCD. OTG or Host only*/
|
/* only valid for HCD. OTG or Host only*/
|
||||||
unsigned int mode;
|
unsigned int mode;
|
||||||
|
|
||||||
int (*phy_init)(unsigned int regbase);
|
int (*phy_init)(void __iomem *regbase);
|
||||||
void (*phy_deinit)(unsigned int regbase);
|
void (*phy_deinit)(void __iomem *regbase);
|
||||||
int (*set_vbus)(unsigned int vbus);
|
int (*set_vbus)(unsigned int vbus);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#ifndef CONFIG_HAVE_CLK
|
||||||
|
/* Dummy stub for clk framework */
|
||||||
|
#define clk_get(dev, id) NULL
|
||||||
|
#define clk_put(clock) do {} while (0)
|
||||||
|
#define clk_enable(clock) do {} while (0)
|
||||||
|
#define clk_disable(clock) do {} while (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in New Issue