arm64: ZynqMP DT changes for v6.5
Various small fixes and cleanups to be aligned with the latest dt-schema. Other major changes are: - Wire mali-400 gpu - Change board name for zcu1275 - Use ethernet-phy-id to handle ETH phy reset properly - Switch to amd.com emails - Update people in DT bindings -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZIHGHgAKCRDKSWXLKUoM IQW2AJ0eRZ5g7SYEg1y/zir6/j5s4RyaiACeO9EQJQ8nKkez73w4uoTBdmmOmlY= =R8F0 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSSEQgACgkQYKtH/8kJ UidFLBAAyqGoiZH0Oh33f6R2nU1+NtH6pTiv4P1z1v8WmIMEvShHk+WhpGllqryC rQKFwMdTIM3L2+zqYvUM5ksysBnbxePVVTV15qZaDpkbV1/Oz/G70EWF0VtGQYxk /OLiMc84WMfaR772Htlb1mmos+9TtSlIwi5f0vkWRCOComPh+vc3u+GedUVBA3M/ 9J0VuymgBeE9H4pGOruTNn1aUxD70hTXiP6Qz7Sv7Eksew80GfGlpNf5EqFM6Lrc /Np03tHVN1lMLDmSbeHRM9ONDQDSEDM2IT0tvN9XH/p1vzKCBpRxHh7/7DVnJdae G/NUGzw9uxZkmvKkXpjTRjYO08GQu6DxwO4G6qBOA9Rr77ibohVdLEvtfpfkwLxO D9oFmi2NZjtyWii5G0xZkfnuB6aU9x2BsPRQduLTfTEYTWoJuoFnmBM/Zhinj0vO 2h0+2PqoT0LpwzcorsbCsk3mHPz0kqc3tNGOd2hGtRvmm2fLxoNbj0OqhLgFLYht OUetwTNqWogKUEzjES526v6ulkAKWkSc0OrXOZkDVyWHCDdEQCMR121GlC6Qo5LK 5OLa2rR5iQ6Er6+N1lzg4AjB5s2k/C40K/pNQIm65uTB4D4YcCvcUABRuRMeR+Nn FlgXDPPyytnZdNhRPt7AhFk10r+AbT8ad3LwjHEQlUT1Mxm+eck= =jqDa -----END PGP SIGNATURE----- Merge tag 'zynqmp-dt-for-v6.5' of https://github.com/Xilinx/linux-xlnx into soc/dt arm64: ZynqMP DT changes for v6.5 Various small fixes and cleanups to be aligned with the latest dt-schema. Other major changes are: - Wire mali-400 gpu - Change board name for zcu1275 - Use ethernet-phy-id to handle ETH phy reset properly - Switch to amd.com emails - Update people in DT bindings * tag 'zynqmp-dt-for-v6.5' of https://github.com/Xilinx/linux-xlnx: (33 commits) dt-bindings: usb: xilinx: Replace Manish by Piyush dt-bindings: xilinx: Remove Rajan, Jolly and Manish arm64: zynqmp: Used fixed-partitions for QSPI in k26 arm64: zynqmp: Add pmu interrupt-affinity arm64: zynqmp: Set qspi tx-buswidth to 4 arm64: zynqmp: Fix usb node drive strength and slew rate arm64: zynqmp: Describe TI phy as ethernet-phy-id arm64: zynqmp: Switch to amd.com emails arm64: zynqmp: Convert kv260-revA overlay to ASCII text dt-bindings: xilinx: Switch xilinx.com emails to amd.com arm64: xilinx: Use zynqmp prefix for SOM dt overlays arm64: zynqmp: Add phase tags marking arm64: zynqmp: Describe bus-width for SD card on KV260 arm64: zynqmp: Enable AMS on SOM and other zcu10x boards arm64: zynqmp: Enable DP driver for SOMs arm64: zynqmp: Setup clock for DP and DPDMA arm64: zynqmp: Switch to ethernet-phy-id in kv260 arm64: zynqmp: Disable USB3.0 for zc1751-xm016-dc2 arm64: zynqmp: Add pinctrl emmc description to SM-K26 arm64: zynqmp: Add gpio labels for modepin gpio ... Link: https://lore.kernel.org/r/CAHTX3d+2s_KmCnd=x5hydGb+LYoznAzYGTizvqqN2NFmrBurfw@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
5e64ee4204
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx Zynq Platforms
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
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|
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description: |
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||||
Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
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|
@ -61,10 +61,10 @@ properties:
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|||
- const: xlnx,zynqmp-zc1254
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- const: xlnx,zynqmp
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- description: Xilinx internal board zc1275
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- description: Xilinx evaluation board zcu1275
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items:
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- const: xlnx,zynqmp-zc1275-revA
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- const: xlnx,zynqmp-zc1275
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- const: xlnx,zynqmp-zcu1275-revA
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- const: xlnx,zynqmp-zcu1275
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- const: xlnx,zynqmp
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- description: Xilinx 96boards compatible board zcu100
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|
|
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Ceva AHCI SATA Controller
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maintainers:
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- Piyush Mehta <piyush.mehta@xilinx.com>
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- Piyush Mehta <piyush.mehta@amd.com>
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description: |
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The Ceva SATA controller mostly conforms to the AHCI interface with some
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx clocking wizard
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||||
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||||
maintainers:
|
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- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
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- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
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description:
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The clocking wizard is a soft ip clocking block of Xilinx versal. It
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|
|
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@ -7,9 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Versal clock controller
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maintainers:
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- Michal Simek <michal.simek@xilinx.com>
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- Jolly Shah <jolly.shah@xilinx.com>
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- Rajan Vaja <rajan.vaja@xilinx.com>
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- Michal Simek <michal.simek@amd.com>
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description: |
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The clock controller is a hardware block of Xilinx versal clock tree. It
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@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx ZynqMP AES-GCM Hardware Accelerator
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maintainers:
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- Kalyani Akula <kalyani.akula@xilinx.com>
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- Michal Simek <michal.simek@xilinx.com>
|
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- Kalyani Akula <kalyani.akula@amd.com>
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- Michal Simek <michal.simek@amd.com>
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description: |
|
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The ZynqMP AES-GCM hardened cryptographic accelerator is used to
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx firmware driver
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maintainers:
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- Nava kishore Manne <nava.manne@xilinx.com>
|
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- Nava kishore Manne <nava.kishore.manne@amd.com>
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|
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description: The zynqmp-firmware node describes the interface to platform
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firmware. ZynqMP has an interface to communicate with secure firmware.
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|
|
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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|||
title: Xilinx Zynq FPGA Manager
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|
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maintainers:
|
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- Michal Simek <michal.simek@xilinx.com>
|
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- Michal Simek <michal.simek@amd.com>
|
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|
||||
properties:
|
||||
compatible:
|
||||
|
|
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|||
|
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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|||
title: Xilinx Versal FPGA driver.
|
||||
|
||||
maintainers:
|
||||
- Nava kishore Manne <nava.manne@xilinx.com>
|
||||
- Nava kishore Manne <nava.kishore.manne@amd.com>
|
||||
|
||||
description: |
|
||||
Device Tree Versal FPGA bindings for the Versal SoC, controlled
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
|
||||
|
||||
maintainers:
|
||||
- Nava kishore Manne <navam@xilinx.com>
|
||||
- Nava kishore Manne <nava.kishore.manne@amd.com>
|
||||
|
||||
description: |
|
||||
Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx Zynq GPIO controller
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx AXI GPIO controller
|
||||
|
||||
maintainers:
|
||||
- Neeli Srinivas <srinivas.neeli@xilinx.com>
|
||||
- Neeli Srinivas <srinivas.neeli@amd.com>
|
||||
|
||||
description:
|
||||
The AXI GPIO design provides a general purpose input/output interface
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ description:
|
|||
PS_MODE). Every pin can be configured as input/output.
|
||||
|
||||
maintainers:
|
||||
- Piyush Mehta <piyush.mehta@xilinx.com>
|
||||
- Piyush Mehta <piyush.mehta@amd.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ properties:
|
|||
- rockchip,rk3228-mali
|
||||
- samsung,exynos4210-mali
|
||||
- stericsson,db8500-mali
|
||||
- xlnx,zynqmp-mali
|
||||
- const: arm,mali-400
|
||||
- items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Cadence I2C controller
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ description: |
|
|||
+------------------------------------------+
|
||||
|
||||
maintainers:
|
||||
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
|
||||
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx MIPI CSI-2 Receiver Subsystem
|
||||
|
||||
maintainers:
|
||||
- Vishal Sagar <vishal.sagar@xilinx.com>
|
||||
- Vishal Sagar <vishal.sagar@amd.com>
|
||||
|
||||
description: |
|
||||
The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
|
||||
|
|
|
|||
|
|
@ -8,8 +8,7 @@ title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
|
|||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Manish Narani <manish.narani@xilinx.com>
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
description: |
|
||||
Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
|
||||
|
|
|
|||
|
|
@ -8,8 +8,7 @@ title: Zynq A05 DDR Memory Controller
|
|||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Manish Narani <manish.narani@xilinx.com>
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
description:
|
||||
The Zynq DDR ECC controller has an optional ECC support in half-bus width
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: CPM Host Controller device tree for Xilinx Versal SoCs
|
||||
|
||||
maintainers:
|
||||
- Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
|
||||
- Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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|||
title: Xilinx Zynq Pinctrl
|
||||
|
||||
maintainers:
|
||||
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
|
||||
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
|
||||
|
||||
description: |
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
|
|
|
|||
|
|
@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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|||
title: Xilinx ZynqMP Pinctrl
|
||||
|
||||
maintainers:
|
||||
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
|
||||
- Rajan Vaja <rajan.vaja@xilinx.com>
|
||||
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
|
||||
|
||||
description: |
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx Zynq MPSoC Power Management
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
description: |
|
||||
The zynqmp-power node describes the power management configurations.
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ description:
|
|||
The RTC controller has separate IRQ lines for seconds and alarm.
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
allOf:
|
||||
- $ref: rtc.yaml#
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Cadence UART Controller
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Cadence SPI controller
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
allOf:
|
||||
- $ref: spi-controller.yaml#
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx SPI controller
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
allOf:
|
||||
- $ref: spi-controller.yaml#
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
allOf:
|
||||
- $ref: spi-controller.yaml#
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ allOf:
|
|||
- $ref: spi-controller.yaml#
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
# Everything else is described in the common file
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Cadence TTC - Triple Timer Counter
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx SuperSpeed DWC3 USB SoC controller
|
||||
|
||||
maintainers:
|
||||
- Manish Narani <manish.narani@xilinx.com>
|
||||
- Piyush Mehta <piyush.mehta@amd.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx udc controller
|
||||
|
||||
maintainers:
|
||||
- Manish Narani <manish.narani@xilinx.com>
|
||||
- Piyush Mehta <piyush.mehta@amd.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Xilinx AXI/PLB softcore and window Watchdog Timer
|
||||
|
||||
maintainers:
|
||||
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
|
||||
- Srinivas Neeli <srinivas.neeli@xilinx.com>
|
||||
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
|
||||
- Srinivas Neeli <srinivas.neeli@amd.com>
|
||||
|
||||
description:
|
||||
The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@
|
|||
dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
|
||||
|
|
@ -17,16 +16,17 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
|
|||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu1275-revA.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb
|
||||
|
||||
sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
|
||||
sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
|
||||
smk-k26-revA-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
|
||||
smk-k26-revA-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
|
||||
zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
|
||||
zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
|
||||
zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
|
||||
zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
|
||||
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revB.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revB.dtb
|
||||
zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
|
||||
zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
|
||||
zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
|
||||
zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* (C) Copyright 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
|
|
@ -2,38 +2,44 @@
|
|||
/*
|
||||
* Clock specification for Xilinx ZynqMP
|
||||
*
|
||||
* (C) Copyright 2017 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
|
||||
/ {
|
||||
pss_ref_clk: pss_ref_clk {
|
||||
bootph-all;
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <33333333>;
|
||||
};
|
||||
|
||||
video_clk: video_clk {
|
||||
bootph-all;
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
|
||||
pss_alt_ref_clk: pss_alt_ref_clk {
|
||||
bootph-all;
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
gt_crx_ref_clk: gt_crx_ref_clk {
|
||||
bootph-all;
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <108000000>;
|
||||
};
|
||||
|
||||
aux_ref_clk: aux_ref_clk {
|
||||
bootph-all;
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
|
|
@ -42,6 +48,7 @@
|
|||
|
||||
&zynqmp_firmware {
|
||||
zynqmp_clk: clock-controller {
|
||||
bootph-all;
|
||||
#clock-cells = <1>;
|
||||
compatible = "xlnx,zynqmp-clk";
|
||||
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
|
||||
|
|
@ -95,6 +102,10 @@
|
|||
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan1 {
|
||||
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
|
@ -181,10 +192,12 @@
|
|||
|
||||
&sdhci0 {
|
||||
clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
assigned-clocks = <&zynqmp_clk SDIO0_REF>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
assigned-clocks = <&zynqmp_clk SDIO1_REF>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
|
|
@ -241,10 +254,14 @@
|
|||
|
||||
&zynqmp_dpdma {
|
||||
clocks = <&zynqmp_clk DPDMA_REF>;
|
||||
assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
clocks = <&zynqmp_clk TOPSW_LSBUS>,
|
||||
<&zynqmp_clk DP_AUDIO_REF>,
|
||||
<&zynqmp_clk DP_VIDEO_REF>;
|
||||
assigned-clocks = <&zynqmp_clk DP_STC_REF>,
|
||||
<&zynqmp_clk DP_AUDIO_REF>,
|
||||
<&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,14 +2,15 @@
|
|||
/*
|
||||
* dts file for KV260 revA Carrier Card
|
||||
*
|
||||
* (C) Copyright 2020 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2020 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* SD level shifter:
|
||||
* "A" – A01 board un-modified (NXP)
|
||||
* "Y" – A01 board modified with legacy interposer (Nexperia)
|
||||
* "Z" – A01 board modified with Diode interposer
|
||||
* "A" - A01 board un-modified (NXP)
|
||||
* "Y" - A01 board modified with legacy interposer (Nexperia)
|
||||
* "Z" - A01 board modified with Diode interposer
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -95,13 +96,15 @@
|
|||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
|
||||
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
assigned-clock-rates = <600000000>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
|
|
@ -132,6 +135,8 @@
|
|||
no-1-8-v;
|
||||
disable-wp;
|
||||
xlnx,mio-bank = <1>;
|
||||
assigned-clock-rates = <187498123>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&gem3 { /* required by spec */
|
||||
|
|
@ -144,16 +149,18 @@
|
|||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
|
||||
reset-delay-us = <2>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
#phy-cells = <1>;
|
||||
reg = <1>;
|
||||
compatible = "ethernet-phy-id2000.a231";
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
reset-assert-us = <100>;
|
||||
reset-deassert-us = <280>;
|
||||
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -259,19 +266,22 @@
|
|||
pinctrl_usb0_default: usb0-default {
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
|
||||
mux {
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for KV260 revA Carrier Card
|
||||
*
|
||||
* (C) Copyright 2020 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2020 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -76,13 +77,15 @@
|
|||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
|
||||
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
assigned-clock-rates = <600000000>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
|
|
@ -115,6 +118,8 @@
|
|||
clk-phase-sd-hs = <126>, <60>;
|
||||
clk-phase-uhs-sdr25 = <120>, <60>;
|
||||
clk-phase-uhs-ddr50 = <126>, <48>;
|
||||
assigned-clock-rates = <187498123>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&gem3 { /* required by spec */
|
||||
|
|
@ -127,16 +132,18 @@
|
|||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
|
||||
reset-delay-us = <2>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
#phy-cells = <1>;
|
||||
reg = <1>;
|
||||
compatible = "ethernet-phy-id2000.a231";
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
reset-assert-us = <100>;
|
||||
reset-deassert-us = <280>;
|
||||
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -242,19 +249,22 @@
|
|||
pinctrl_usb0_default: usb0-default {
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
|
||||
mux {
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* (C) Copyright 2020 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -14,6 +14,7 @@
|
|||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP SM-K26 Rev1/B/A";
|
||||
|
|
@ -55,6 +56,9 @@
|
|||
key-fwuen {
|
||||
label = "fwuen";
|
||||
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <BTN_MISC>;
|
||||
wakeup-source;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -72,109 +76,158 @@
|
|||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
ams {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
|
||||
<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
|
||||
<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
|
||||
<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
|
||||
<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
|
||||
<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
|
||||
<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
|
||||
<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
|
||||
<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
|
||||
<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
|
||||
};
|
||||
};
|
||||
|
||||
&modepin_gpio {
|
||||
label = "modepin";
|
||||
};
|
||||
|
||||
&uart1 { /* MIO36/MIO37 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_sdhci0_default: sdhci0-default {
|
||||
conf {
|
||||
groups = "sdio0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux {
|
||||
groups = "sdio0_0_grp";
|
||||
function = "sdio0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi { /* MIO 0-5 - U143 */
|
||||
status = "okay";
|
||||
flash@0 { /* MT25QU512A */
|
||||
spi_flash: flash@0 { /* MT25QU512A */
|
||||
compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <40000000>; /* 40MHz */
|
||||
partition@0 {
|
||||
label = "Image Selector";
|
||||
reg = <0x0 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "Image Selector Golden";
|
||||
reg = <0x80000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "Persistent Register";
|
||||
reg = <0x100000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@120000 {
|
||||
label = "Persistent Register Backup";
|
||||
reg = <0x120000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@140000 {
|
||||
label = "Open_1";
|
||||
reg = <0x140000 0xC0000>; /* 768KB */
|
||||
};
|
||||
partition@200000 {
|
||||
label = "Image A (FSBL, PMU, ATF, U-Boot)";
|
||||
reg = <0x200000 0xD00000>; /* 13MB */
|
||||
};
|
||||
partition@f00000 {
|
||||
label = "ImgSel Image A Catch";
|
||||
reg = <0xF00000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@f80000 {
|
||||
label = "Image B (FSBL, PMU, ATF, U-Boot)";
|
||||
reg = <0xF80000 0xD00000>; /* 13MB */
|
||||
};
|
||||
partition@1c80000 {
|
||||
label = "ImgSel Image B Catch";
|
||||
reg = <0x1C80000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@1d00000 {
|
||||
label = "Open_2";
|
||||
reg = <0x1D00000 0x100000>; /* 1MB */
|
||||
};
|
||||
partition@1e00000 {
|
||||
label = "Recovery Image";
|
||||
reg = <0x1E00000 0x200000>; /* 2MB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2000000 {
|
||||
label = "Recovery Image Backup";
|
||||
reg = <0x2000000 0x200000>; /* 2MB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2200000 {
|
||||
label = "U-Boot storage variables";
|
||||
reg = <0x2200000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@2220000 {
|
||||
label = "U-Boot storage variables backup";
|
||||
reg = <0x2220000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@2240000 {
|
||||
label = "SHA256";
|
||||
reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2250000 {
|
||||
label = "User";
|
||||
reg = <0x2250000 0x1db0000>; /* 29.5 MB */
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "Image Selector";
|
||||
reg = <0x0 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "Image Selector Golden";
|
||||
reg = <0x80000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "Persistent Register";
|
||||
reg = <0x100000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@120000 {
|
||||
label = "Persistent Register Backup";
|
||||
reg = <0x120000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@140000 {
|
||||
label = "Open_1";
|
||||
reg = <0x140000 0xC0000>; /* 768KB */
|
||||
};
|
||||
partition@200000 {
|
||||
label = "Image A (FSBL, PMU, ATF, U-Boot)";
|
||||
reg = <0x200000 0xD00000>; /* 13MB */
|
||||
};
|
||||
partition@f00000 {
|
||||
label = "ImgSel Image A Catch";
|
||||
reg = <0xF00000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@f80000 {
|
||||
label = "Image B (FSBL, PMU, ATF, U-Boot)";
|
||||
reg = <0xF80000 0xD00000>; /* 13MB */
|
||||
};
|
||||
partition@1c80000 {
|
||||
label = "ImgSel Image B Catch";
|
||||
reg = <0x1C80000 0x80000>; /* 512KB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@1d00000 {
|
||||
label = "Open_2";
|
||||
reg = <0x1D00000 0x100000>; /* 1MB */
|
||||
};
|
||||
partition@1e00000 {
|
||||
label = "Recovery Image";
|
||||
reg = <0x1E00000 0x200000>; /* 2MB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2000000 {
|
||||
label = "Recovery Image Backup";
|
||||
reg = <0x2000000 0x200000>; /* 2MB */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2200000 {
|
||||
label = "U-Boot storage variables";
|
||||
reg = <0x2200000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@2220000 {
|
||||
label = "U-Boot storage variables backup";
|
||||
reg = <0x2220000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@2240000 {
|
||||
label = "SHA256";
|
||||
reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
|
||||
read-only;
|
||||
lock;
|
||||
};
|
||||
partition@2280000 {
|
||||
label = "Secure OS Storage";
|
||||
reg = <0x2280000 0x20000>; /* 128KB */
|
||||
};
|
||||
partition@22A0000 {
|
||||
label = "User";
|
||||
reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci0_default>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
bus-width = <8>;
|
||||
xlnx,mio-bank = <0>;
|
||||
assigned-clock-rates = <187498123>;
|
||||
};
|
||||
|
||||
&spi1 { /* MIO6, 9-11 */
|
||||
|
|
@ -190,17 +243,20 @@
|
|||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
bootph-all;
|
||||
clock-frequency = <400000>;
|
||||
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
eeprom: eeprom@50 { /* u46 - also at address 0x58 */
|
||||
bootph-all;
|
||||
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
|
||||
reg = <0x50>;
|
||||
/* WP pin EE_WP_EN connected to slg7x644092@68 */
|
||||
};
|
||||
|
||||
eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
|
||||
bootph-all;
|
||||
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
|
@ -287,3 +343,114 @@
|
|||
"", "", "", "", "", /* 165 - 169 */
|
||||
"", "", "", ""; /* 170 - 173 */
|
||||
};
|
||||
|
||||
&xilinx_ams {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_pl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpd_watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu_opp_table {
|
||||
opp00 {
|
||||
opp-hz = /bits/ 64 <1333333333>;
|
||||
};
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <666666666>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <444444444>;
|
||||
};
|
||||
opp03 {
|
||||
opp-hz = /bits/ 64 <333333333>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* (C) Copyright 2020 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-sm-k26-revA.dts"
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* (C) Copyright 2017 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@
|
|||
*
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -45,7 +45,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
|
||||
*
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -108,6 +109,9 @@
|
|||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
|
@ -184,19 +188,22 @@
|
|||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -348,7 +355,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
|
||||
*
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -281,19 +282,22 @@
|
|||
|
||||
conf {
|
||||
groups = "usb1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO64", "MIO65", "MIO67";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
|
||||
"MIO72", "MIO73", "MIO74", "MIO75";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -485,8 +489,6 @@
|
|||
&dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* (C) Copyright 2016 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -152,6 +152,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
|
@ -169,7 +173,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>; /* also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@
|
|||
*
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU100 revC
|
||||
*
|
||||
* (C) Copyright 2016 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
* Nathalie Chan King Choy
|
||||
*/
|
||||
|
||||
|
|
@ -58,6 +59,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
iio-hwmon {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
|
||||
<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
|
||||
<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
|
||||
<&xilinx_ams 9>, <&xilinx_ams 10>,
|
||||
<&xilinx_ams 11>, <&xilinx_ams 12>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led-ds2 {
|
||||
|
|
@ -161,6 +171,10 @@
|
|||
"", "", "", "";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "gpio";
|
||||
|
|
@ -419,19 +433,22 @@
|
|||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -443,19 +460,22 @@
|
|||
|
||||
conf {
|
||||
groups = "usb1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO64", "MIO65", "MIO67";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
|
||||
"MIO72", "MIO73", "MIO74", "MIO75";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -541,6 +561,7 @@
|
|||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
|
||||
/delete-property/ reset-gpios;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
|
|
@ -556,6 +577,7 @@
|
|||
pinctrl-0 = <&pinctrl_usb1_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
|
||||
reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&dwc3_1 {
|
||||
|
|
@ -568,6 +590,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&xilinx_ams {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* (C) Copyright 2016 - 2018, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-zcu102-revB.dts"
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* (C) Copyright 2016 - 2020, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-zcu102-rev1.0.dts"
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU102 RevA
|
||||
*
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -200,13 +201,19 @@
|
|||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@21 {
|
||||
reg = <21>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: ethernet-phy@21 {
|
||||
#phy-cells = <1>;
|
||||
compatible = "ethernet-phy-id2000.a231";
|
||||
reg = <21>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -216,6 +223,10 @@
|
|||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -772,19 +783,22 @@
|
|||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -943,7 +957,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
|
|
@ -1013,6 +1027,18 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&xilinx_ams {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_pl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU102 RevB
|
||||
*
|
||||
* (C) Copyright 2016 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-zcu102-revA.dts"
|
||||
|
|
@ -16,16 +17,20 @@
|
|||
|
||||
&gem3 {
|
||||
phy-handle = <&phyc>;
|
||||
phyc: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
|
||||
mdio: mdio {
|
||||
phyc: ethernet-phy@c {
|
||||
#phy-cells = <0x1>;
|
||||
compatible = "ethernet-phy-id2000.a231";
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
/* Cleanup from RevA */
|
||||
/delete-node/ ethernet-phy@21;
|
||||
};
|
||||
/* Cleanup from RevA */
|
||||
/delete-node/ ethernet-phy@21;
|
||||
};
|
||||
|
||||
/* Fix collision with u61 */
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU104
|
||||
*
|
||||
* (C) Copyright 2017 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -109,12 +110,19 @@
|
|||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: ethernet-phy@c {
|
||||
#phy-cells = <1>;
|
||||
compatible = "ethernet-phy-id2000.a231";
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -122,6 +130,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -398,20 +410,22 @@
|
|||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -430,7 +444,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
|
|
@ -497,6 +511,18 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&xilinx_ams {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_pl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU104
|
||||
*
|
||||
* (C) Copyright 2017 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -114,12 +115,19 @@
|
|||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: ethernet-phy@c {
|
||||
#phy-cells = <1>;
|
||||
compatible = "ethernet-phy-id2000.a231";
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -127,6 +135,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -410,20 +422,22 @@
|
|||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -442,7 +456,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
|
|
@ -509,6 +523,18 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&xilinx_ams {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_pl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU106
|
||||
*
|
||||
* (C) Copyright 2016 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -212,12 +213,19 @@
|
|||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: ethernet-phy@c {
|
||||
#phy-cells = <1>;
|
||||
reg = <0xc>;
|
||||
compatible = "ethernet-phy-id2000.a231";
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -227,6 +235,10 @@
|
|||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -782,19 +794,22 @@
|
|||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -949,7 +964,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,9 +2,10 @@
|
|||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU111
|
||||
*
|
||||
* (C) Copyright 2017 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2022, Xilinx, Inc.
|
||||
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -172,12 +173,19 @@
|
|||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy0: ethernet-phy@c {
|
||||
#phy-cells = <1>;
|
||||
compatible = "ethernet-phy-id2000.a231";
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -187,6 +195,10 @@
|
|||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -648,19 +660,22 @@
|
|||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
drive-strength = <12>;
|
||||
slew-rate = <SLEW_RATE_FAST>;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -779,7 +794,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@
|
|||
*
|
||||
* (C) Copyright 2017 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -14,8 +14,8 @@
|
|||
#include "zynqmp-clk-ccf.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZC1275 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
|
||||
model = "ZynqMP ZCU1275 RevA";
|
||||
compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
|
|
@ -47,7 +47,7 @@
|
|||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
*
|
||||
* (C) Copyright 2014 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
|
|
@ -118,6 +118,7 @@
|
|||
};
|
||||
|
||||
zynqmp_ipi: zynqmp_ipi {
|
||||
bootph-all;
|
||||
compatible = "xlnx,zynqmp-ipi-mailbox";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 35 4>;
|
||||
|
|
@ -126,7 +127,8 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ipi_mailbox_pmu1: mailbox@ff990400 {
|
||||
ipi_mailbox_pmu1: mailbox@ff9905c0 {
|
||||
bootph-all;
|
||||
reg = <0x0 0xff9905c0 0x0 0x20>,
|
||||
<0x0 0xff9905e0 0x0 0x20>,
|
||||
<0x0 0xff990e80 0x0 0x20>,
|
||||
|
|
@ -143,6 +145,7 @@
|
|||
dcc: dcc {
|
||||
compatible = "arm,dcc";
|
||||
status = "disabled";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
pmu {
|
||||
|
|
@ -152,6 +155,10 @@
|
|||
<0 144 4>,
|
||||
<0 145 4>,
|
||||
<0 146 4>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
psci {
|
||||
|
|
@ -164,8 +171,10 @@
|
|||
compatible = "xlnx,zynqmp-firmware";
|
||||
#power-domain-cells = <1>;
|
||||
method = "smc";
|
||||
bootph-all;
|
||||
|
||||
zynqmp_power: zynqmp-power {
|
||||
bootph-all;
|
||||
compatible = "xlnx,zynqmp-power";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 35 4>;
|
||||
|
|
@ -245,6 +254,7 @@
|
|||
|
||||
amba: axi {
|
||||
compatible = "simple-bus";
|
||||
bootph-all;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -400,7 +410,6 @@
|
|||
|
||||
gic: interrupt-controller@f9010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x0 0xf9010000 0x0 0x10000>,
|
||||
<0x0 0xf9020000 0x0 0x20000>,
|
||||
|
|
@ -411,6 +420,18 @@
|
|||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
gpu: gpu@fd4b0000 {
|
||||
status = "disabled";
|
||||
compatible = "xlnx,zynqmp-mali", "arm,mali-400";
|
||||
reg = <0x0 0xfd4b0000 0x0 0x10000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 132 4>, <0 132 4>, <0 132 4>,
|
||||
<0 132 4>, <0 132 4>, <0 132 4>;
|
||||
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
|
||||
clock-names = "bus", "core";
|
||||
power-domains = <&zynqmp_firmware PD_GPU>;
|
||||
};
|
||||
|
||||
/* LPDDMA default allows only secured access. inorder to enable
|
||||
* These dma channels, Users should ensure that these dma
|
||||
* Channels are allowed for non secure access.
|
||||
|
|
@ -602,7 +623,6 @@
|
|||
gpio: gpio@ff0a0000 {
|
||||
compatible = "xlnx,zynqmp-gpio-1.0";
|
||||
status = "disabled";
|
||||
#address-cells = <0>;
|
||||
#gpio-cells = <0x2>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -674,6 +694,7 @@
|
|||
};
|
||||
|
||||
qspi: spi@ff0f0000 {
|
||||
bootph-all;
|
||||
compatible = "xlnx,zynqmp-qspi-1.0";
|
||||
status = "disabled";
|
||||
clock-names = "ref_clk", "pclk";
|
||||
|
|
@ -720,6 +741,7 @@
|
|||
};
|
||||
|
||||
sdhci0: mmc@ff160000 {
|
||||
bootph-all;
|
||||
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -730,9 +752,11 @@
|
|||
#clock-cells = <1>;
|
||||
clock-output-names = "clk_out_sd0", "clk_in_sd0";
|
||||
power-domains = <&zynqmp_firmware PD_SD_0>;
|
||||
resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
|
||||
};
|
||||
|
||||
sdhci1: mmc@ff170000 {
|
||||
bootph-all;
|
||||
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -743,6 +767,7 @@
|
|||
#clock-cells = <1>;
|
||||
clock-output-names = "clk_out_sd1", "clk_in_sd1";
|
||||
power-domains = <&zynqmp_firmware PD_SD_1>;
|
||||
resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
|
||||
};
|
||||
|
||||
smmu: iommu@fd800000 {
|
||||
|
|
@ -824,6 +849,7 @@
|
|||
};
|
||||
|
||||
uart0: serial@ff000000 {
|
||||
bootph-all;
|
||||
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -834,6 +860,7 @@
|
|||
};
|
||||
|
||||
uart1: serial@ff010000 {
|
||||
bootph-all;
|
||||
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -928,13 +955,13 @@
|
|||
#io-channel-cells = <1>;
|
||||
ranges = <0 0 0xffa50800 0x800>;
|
||||
|
||||
ams_ps: ams_ps@0 {
|
||||
ams_ps: ams-ps@0 {
|
||||
compatible = "xlnx,zynqmp-ams-ps";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x400>;
|
||||
};
|
||||
|
||||
ams_pl: ams_pl@400 {
|
||||
ams_pl: ams-pl@400 {
|
||||
compatible = "xlnx,zynqmp-ams-pl";
|
||||
status = "disabled";
|
||||
reg = <0x400 0x400>;
|
||||
|
|
@ -955,6 +982,7 @@
|
|||
};
|
||||
|
||||
zynqmp_dpsub: display@fd4a0000 {
|
||||
bootph-all;
|
||||
compatible = "xlnx,zynqmp-dpsub-1.7";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xfd4a0000 0x0 0x1000>,
|
||||
|
|
|
|||
Loading…
Reference in New Issue