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dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property 

The GIC v3 specifications allow redistributors and ITSes interconnect
ports used to access memory to be wired up in a way that makes the
respective initiators/memory observers non-coherent.

Add the standard dma-noncoherent property to the GICv3 bindings to
allow firmware to describe the redistributors/ITSes components and
interconnect ports behaviour in system designs where the redistributors
and ITSes are not coherent with the CPU.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20231006125929.48591-2-lpieralisi@kernel.org
This commit is contained in:
Lorenzo Pieralisi 2023-10-06 14:59:25 +02:00 committed by Marc Zyngier
parent 977f7c2b27
commit 5e5c636c69
1 changed files with 12 additions and 0 deletions
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Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
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@ -106,6 +106,12 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint32
maximum: 4096 maximum: 4096
dma-noncoherent:
description:
Present if the GIC redistributors permit programming shareability
and cacheability attributes but are connected to a non-coherent
downstream interconnect.
msi-controller: msi-controller:
description: description:
Only present if the Message Based Interrupt functionality is Only present if the Message Based Interrupt functionality is
@ -193,6 +199,12 @@ patternProperties:
compatible: compatible:
const: arm,gic-v3-its const: arm,gic-v3-its
dma-noncoherent:
description:
Present if the GIC ITS permits programming shareability and
cacheability attributes but is connected to a non-coherent
downstream interconnect.
msi-controller: true msi-controller: true
"#msi-cells": "#msi-cells":