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iommu/vt-d: Enable upto 57 bits of domain address width 

Update the IOMMU default domain address width to 57 bits. This would
enable the IOMMU to do upto 5-levels of paging for second level
translations - IOVA translation requests without PASID.

Even though the maximum supported address width is being increased to
57, __iommu_calculate_agaw() would set the actual supported address
width to the maximum support available in IOMMU hardware.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Sohil Mehta 2017-12-20 11:59:24 -08:00 committed by Joerg Roedel
parent 9d2e6505f6
commit 5e3b4a15dd
1 changed files with 1 additions and 1 deletions
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2
drivers/iommu/intel-iommu.c
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@ -64,7 +64,7 @@
#define IOAPIC_RANGE_END (0xfeefffff) #define IOAPIC_RANGE_END (0xfeefffff)
#define IOVA_START_ADDR (0x1000) #define IOVA_START_ADDR (0x1000)
#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 57
#define MAX_AGAW_WIDTH 64 #define MAX_AGAW_WIDTH 64
#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)