Qualcomm ARM64 DeviceTree fixes for v6.6
This fixes an error with an incorrect gpio-ranges preventing the PMIC GPIO instances from being registered on SA877P, and fixes a regression from a refactoring of the top-level clocks node that caused divclocks to no longer probe on a few of the MSM8996 devices. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmUsKLQVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FXC8P/1myl64TT+FCvlKbE9qwiFQYd30J zFRSH38P3XLGZ15QEg8raJdMrGLO319fISh30mepYfAdJLfxaP4qY2okT9vOLbsC SlG9QwJScE87t88lJMb/3m7l/Vo9yy1PNjcE4AUPKwdOqMR3x6nzjqKAMVJIGwkh T20LSqnZh2hpvSV2dtCgSvs3CTqCdKusY5EC7zQhsPds0DCjeujhBMiQOmjiS2MZ TWY8pX7mqZX9gV5UYYPmCbql+v8TLPgrQ3E3MCRWCpsqIcIEClGG9vPfA7JrmUOo aHL1lcxDvhxrjn5Bxutny5sDQAKuSzOoCSRJ8m5Xw7IbVlR8PeP9ESBLhw/LaFuP Ej5atetgpqwARueeZgn6CpwVVXFlD/ruuhq8QRCjrRtpv9NeUN84jVv2eBd6Nzvf j0KVUdeem1dXmzbFZ+iPkQuwW9fuiElp2vg8Anlz14trVVYpbOVQbSkhQVxxHhw2 MRymdfBuwUt/IfRtO4w0llqww3W2oPRLHYkmmkgZQJmaRipuCeAXklnuKOzNde+I BTENX32wgj1+U7CBWeFzryXfB+iKSuu/03py815zAHiTksKKmgU11qT7V9pVp5Bw LSPncRSseJO3NczZenTVwkX6aQf2zaonEBlL/EVJGi5B9ye4jRKO+gfMjU00fVAs LrjkGB7bDUyRloiN =EGy8 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmUtRiEACgkQYKtH/8kJ UicIEg//cbTJuU0JlL5AOsjxY9mai74oDeGh59a4et3L7BDh/pqfNySwHmIl3F0s 5Lk+k1cJ+xoMFRGfOpGNYVjR1jhB+UtyiiXA+o6jQFGI+jVHuGczF62W555Z8wAI IYnjL4N8Ey1w8nO9nsuvj6anMZ1s6G+pjbhVFK3LZBr0RTra6n5yw5FnWZb3VWdg s9C3msyp/do+eJK+nmy4+RE/+DdLEJxyPXADSKRN83RI3obvhVDj1VnjjV8ewHbE cwPLmi9rFIeuAx4GPR2SM+pZVk6BZu4Yhpz3xtclTvek3geg44JtEUhruVmJOa0K 3w7M5CHg1BNWSQssKJTprFJ54s6Ss75L5vfpLtS9MaqcGcWA8TYy+aUOMQ5Ql1Ie ZGJUD2vMYvafrTyACYyZN1nZo5cZFofTKdu4Ty7XlmVs+7n+k9k4TlOidc4hOXSG djOMxG27tkMmut+Y9VLqobbRu1WB1PcOvrnh6e/s7L+m3Z6NyJO9eeyKAbgbX2+n MnHQ0rAWJEi+r5+5IWRwyJogN2x9zBzYlnaDJeOT9TarTvlWaLd+tX0Ubw6tfHQP FHPzb2Nl4OTOmwV8lZgxQTIc2bOpBq7OPxvGV1AXcOXUK7iwmQPOsHbWd0DAvrUZ Dv4+x0DKAXH3EpbGAI3dzQlbiwjfo31nglS6uNc3hKZX5gDaynk= =O/dR -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-fixes-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes Qualcomm ARM64 DeviceTree fixes for v6.6 This fixes an error with an incorrect gpio-ranges preventing the PMIC GPIO instances from being registered on SA877P, and fixes a regression from a refactoring of the top-level clocks node that caused divclocks to no longer probe on a few of the MSM8996 devices. * tag 'qcom-arm64-fixes-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: dts: qcom: msm8996-xiaomi: fix missing clock populate arm64: dts: qcom: apq8096-db820c: fix missing clock populate arm64: dts: qcom: sa8775p: correct PMIC GPIO label in gpio-ranges Link: https://lore.kernel.org/r/20231015180112.853805-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
5e24617f66
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@ -62,25 +62,23 @@
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stdout-path = "serial0:115200n8";
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};
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clocks {
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divclk4: divclk4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "divclk4";
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div1_mclk: divclk1 {
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compatible = "gpio-gate-clock";
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pinctrl-0 = <&audio_mclk>;
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pinctrl-names = "default";
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clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
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#clock-cells = <0>;
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enable-gpios = <&pm8994_gpios 15 0>;
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};
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pinctrl-names = "default";
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pinctrl-0 = <&divclk4_pin_a>;
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};
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divclk4: divclk4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "divclk4";
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div1_mclk: divclk1 {
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compatible = "gpio-gate-clock";
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pinctrl-0 = <&audio_mclk>;
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pinctrl-names = "default";
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clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
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#clock-cells = <0>;
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enable-gpios = <&pm8994_gpios 15 0>;
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};
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pinctrl-names = "default";
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pinctrl-0 = <&divclk4_pin_a>;
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};
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gpio-keys {
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@ -11,26 +11,24 @@
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#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
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/ {
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clocks {
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divclk1_cdc: divclk1 {
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compatible = "gpio-gate-clock";
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clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
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#clock-cells = <0>;
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enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>;
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divclk1_cdc: divclk1 {
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compatible = "gpio-gate-clock";
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clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
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#clock-cells = <0>;
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enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&divclk1_default>;
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};
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pinctrl-names = "default";
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pinctrl-0 = <&divclk1_default>;
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};
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divclk4: divclk4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "divclk4";
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divclk4: divclk4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "divclk4";
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pinctrl-names = "default";
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pinctrl-0 = <&divclk4_pin_a>;
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};
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pinctrl-names = "default";
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pinctrl-0 = <&divclk4_pin_a>;
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};
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gpio-keys {
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@ -20,16 +20,14 @@
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qcom,pmic-id = <0x20009 0x2000a 0x00 0x00>;
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qcom,board-id = <31 0>;
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clocks {
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divclk2_haptics: divclk2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "divclk2";
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divclk2_haptics: divclk2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "divclk2";
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pinctrl-names = "default";
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pinctrl-0 = <&divclk2_pin_a>;
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};
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pinctrl-names = "default";
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pinctrl-0 = <&divclk2_pin_a>;
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};
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};
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@ -173,7 +173,7 @@
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compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
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reg = <0x8800>;
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gpio-controller;
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gpio-ranges = <&pmm8654au_2_gpios 0 0 12>;
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gpio-ranges = <&pmm8654au_1_gpios 0 0 12>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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