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ARM: mvebu: Add MBus to Armada 370/XP device tree 

The Armada 370/XP SoC family has a completely configurable address
space handled by the MBus controller.

This patch introduces the device tree layout of MBus, making the
'soc' node as mbus-compatible.
Since every peripheral/controller is a child of this 'soc' node,
this makes all of them sit behind the mbus, thus describing the
hardware accurately.

A translation entry has been added for the internal-regs mapping.
This can't be done in the common armada-370-xp.dtsi because A370
and AXP have different addressing width.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Ezequiel Garcia 2013-07-26 10:17:57 -03:00 committed by Jason Cooper
parent 38149887ef
commit 5e12a613ce
9 changed files with 23 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/armada-370-db.dts
View File

@ -30,6 +30,8 @@
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {
clock-frequency = <200000000>;

2
arch/arm/boot/dts/armada-370-mirabox.dts
View File

@ -25,6 +25,8 @@
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {
clock-frequency = <200000000>;

2
arch/arm/boot/dts/armada-370-rd.dts
View File

@ -28,6 +28,8 @@
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {
clock-frequency = <200000000>;

15
arch/arm/boot/dts/armada-370-xp.dtsi
View File

@ -18,6 +18,8 @@
/include/ "skeleton64.dtsi"
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
model = "Marvell Armada 370 and XP SoC";
compatible = "marvell,armada-370-xp";
@ -38,18 +40,21 @@
};
soc {
#address-cells = <1>;
#address-cells = <2>;
#size-cells = <1>;
compatible = "simple-bus";
controller = <&mbusc>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";

4
arch/arm/boot/dts/armada-370.dtsi
View File

@ -29,8 +29,8 @@
};
soc {
ranges = <0 0xd0000000 0x0100000 /* internal registers */
0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
compatible = "marvell,armada370-mbus", "simple-bus";
internal-regs {
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";

4
arch/arm/boot/dts/armada-xp-db.dts
View File

@ -30,9 +30,7 @@
};
soc {
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {

4
arch/arm/boot/dts/armada-xp-gp.dts
View File

@ -39,9 +39,7 @@
};
soc {
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>;
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {

4
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View File

@ -27,9 +27,7 @@
};
soc {
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>;
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {

2
arch/arm/boot/dts/armada-xp.dtsi
View File

@ -27,6 +27,8 @@
};
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
internal-regs {
L2: l2-cache {
compatible = "marvell,aurora-system-cache";