arm64: dts: sparx5: Add spi-nand devices
This patch add spi-nand DT nodes to the applicable Sparx5 boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
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@ -206,6 +206,26 @@
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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cs1_pins: cs1-pins {
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pins = "GPIO_16";
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function = "si";
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};
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cs2_pins: cs2-pins {
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pins = "GPIO_17";
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function = "si";
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};
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cs3_pins: cs3-pins {
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pins = "GPIO_18";
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function = "si";
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};
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si2_pins: si2-pins {
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pins = "GPIO_39", "GPIO_40", "GPIO_41";
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function = "si2";
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};
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uart_pins: uart-pins {
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pins = "GPIO_10", "GPIO_11";
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function = "uart";
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@ -0,0 +1,31 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*/
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&gpio {
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cs14_pins: cs14-pins {
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pins = "GPIO_44";
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function = "si";
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};
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};
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&spi0 {
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pinctrl-0 = <&si2_pins>;
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pinctrl-names = "default";
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spi@e {
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compatible = "spi-mux";
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mux-controls = <&mux>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <14>; /* CS14 */
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spi-flash@6 {
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compatible = "spi-nand";
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pinctrl-0 = <&cs14_pins>;
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pinctrl-names = "default";
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reg = <0x6>; /* SPI2 */
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spi-max-frequency = <42000000>;
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rx-sample-delay-ns = <7>; /* Tune for speed */
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};
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};
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};
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@ -53,6 +53,20 @@
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reg = <0x9>; /* SPI */
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};
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};
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spi@1 {
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compatible = "spi-mux";
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mux-controls = <&mux 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>; /* CS1 */
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spi-flash@9 {
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compatible = "spi-nand";
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pinctrl-0 = <&cs1_pins>;
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pinctrl-names = "default";
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spi-max-frequency = <8000000>;
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reg = <0x9>; /* SPI */
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};
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};
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};
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&i2c1 {
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@ -5,6 +5,7 @@
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/dts-v1/;
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#include "sparx5_pcb134_board.dtsi"
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#include "sparx5_nand.dtsi"
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/ {
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model = "Sparx5 PCB134 Reference Board (NAND)";
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@ -5,6 +5,7 @@
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/dts-v1/;
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#include "sparx5_pcb135_board.dtsi"
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#include "sparx5_nand.dtsi"
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/ {
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model = "Sparx5 PCB135 Reference Board (NAND)";
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