ARM: EXYNOS: Support Suspend/Resume for EXYNOS4412
This patch provides the suspend/resume support for EXYNOS4412. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -177,7 +177,7 @@
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#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
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/* Only for EXYNOS4212 */
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/* Only for EXYNOS4x12 */
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#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
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#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
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#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
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@ -218,4 +218,12 @@
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#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
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#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
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/* Only for EXYNOS4412 */
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#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
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#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
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#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
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#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
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#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
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#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
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#endif /* __ASM_ARCH_REGS_PMU_H */
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@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void)
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tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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if (soc_is_exynos4212()) {
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if (soc_is_exynos4212() || soc_is_exynos4412()) {
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tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
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tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
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S5P_USE_STANDBYWFE_ISP_ARM);
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@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
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{ PMU_TABLE_END,},
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};
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static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
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static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
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{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
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{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
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{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
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@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
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{ PMU_TABLE_END,},
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};
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static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
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{ S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
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{ S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
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{ S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
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{ S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
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{ S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
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{ S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
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{ PMU_TABLE_END,},
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};
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void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
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{
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unsigned int i;
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@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
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for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
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__raw_writel(exynos4_pmu_config[i].val[mode],
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exynos4_pmu_config[i].reg);
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if (soc_is_exynos4412()) {
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for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
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__raw_writel(exynos4412_pmu_config[i].val[mode],
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exynos4412_pmu_config[i].reg);
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}
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}
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static int __init exynos4_pmu_init(void)
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@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void)
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if (soc_is_exynos4210()) {
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exynos4_pmu_config = exynos4210_pmu_config;
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pr_info("EXYNOS4210 PMU Initialize\n");
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} else if (soc_is_exynos4212()) {
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exynos4_pmu_config = exynos4212_pmu_config;
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pr_info("EXYNOS4212 PMU Initialize\n");
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} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
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exynos4_pmu_config = exynos4x12_pmu_config;
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pr_info("EXYNOS4x12 PMU Initialize\n");
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} else {
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pr_info("EXYNOS4: PMU not supported\n");
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}
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