drm/i915/skl: Deinit/init the display at suspend/resume
We need to re-init the display hardware when going out of suspend. This
includes:
- Hooking the PCH to the reset logic
- Restoring CDCDLK
- Enabling the DDB power
Among those, only the CDCDLK one is a bit tricky. There's some
complexity in that:
- DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
of supported frequencies. As eDP also uses DPLL0 for its link rate,
once DPLL0 is on, we restrict the possible eDP link rates the chosen
VCO.
- CDCLK also limits the bandwidth available to push pixels.
So, as a first step, this commit restore what the BIOS set, until I can
do more testing.
In case that's of interest for the reviewer, I've unit tested the
function that derives the decimal frequency field:
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
static const struct dpll_freq {
unsigned int freq;
unsigned int decimal;
} freqs[] = {
{ .freq = 308570, .decimal = 0b01001100111},
{ .freq = 337500, .decimal = 0b01010100001},
{ .freq = 432000, .decimal = 0b01101011110},
{ .freq = 450000, .decimal = 0b01110000010},
{ .freq = 540000, .decimal = 0b10000110110},
{ .freq = 617140, .decimal = 0b10011010000},
{ .freq = 675000, .decimal = 0b10101000100},
};
static void intbits(unsigned int v)
{
int i;
for(i = 10; i >= 0; i--)
putchar('0' + ((v >> i) & 1));
}
static unsigned int freq_decimal(unsigned int freq /* in kHz */)
{
return (freq - 1000) / 500;
}
static void test_freq(const struct dpll_freq *entry)
{
unsigned int decimal = freq_decimal(entry->freq);
printf("freq: %d, expected: ", entry->freq);
intbits(entry->decimal);
printf(", got: ");
intbits(decimal);
putchar('\n');
assert(decimal == entry->decimal);
}
int main(int argc, char **argv)
{
int i;
for (i = 0; i < ARRAY_SIZE(freqs); i++)
test_freq(&freqs[i]);
return 0;
}
v2:
- Rebase on top of -nightly
- Use (freq - 1000) / 500 for the decimal frequency (Ville)
- Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
- Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
be consistent with the BXT code (Ville)
- Store boot CDCLK in ddi_pll_init (Ville)
- Merge dev_priv's skl_boot_cdclk into cdclk_freq
- Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
- Replace various '0' by SKL_DPLL0 to be a bit more explicit that
we're programming DPLL0
- Busy poll the PCU before doing the frequency change. It takes about
3/4 cycles, each separated by 10us, to get the ACK from the CPU
(Ville)
v3:
- Restore dev_priv->skl_boot_cdclk, leaving unification with
dev_priv->cdclk_freq for a later patch (Daniel, Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau
Daniel Vetter
parent
e61b995841
commit
5d96d8afcf
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@ -1047,6 +1047,8 @@ static int skl_suspend_complete(struct drm_i915_private *dev_priv)
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*/
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intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED);
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skl_uninit_cdclk(dev_priv);
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return 0;
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}
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@ -1093,6 +1095,7 @@ static int skl_resume_prepare(struct drm_i915_private *dev_priv)
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{
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struct drm_device *dev = dev_priv->dev;
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skl_init_cdclk(dev_priv);
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intel_csr_load_program(dev);
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return 0;
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@ -1705,6 +1705,7 @@ struct drm_i915_private {
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int num_fence_regs; /* 8 on pre-965, 16 otherwise */
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unsigned int fsb_freq, mem_freq, is_ddr3;
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unsigned int skl_boot_cdclk;
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unsigned int cdclk_freq;
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unsigned int hpll_freq;
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@ -6699,6 +6699,9 @@ enum skl_disp_power_wells {
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#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
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#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
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#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
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#define SKL_PCODE_CDCLK_CONTROL 0x7
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#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
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#define SKL_CDCLK_READY_FOR_CHANGE 0x1
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#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
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#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
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#define GEN6_READ_OC_PARAMS 0xc
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@ -2510,6 +2510,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t val = I915_READ(LCPLL_CTL);
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int cdclk_freq;
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if (IS_SKYLAKE(dev))
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skl_shared_dplls_init(dev_priv);
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@ -2518,12 +2519,15 @@ void intel_ddi_pll_init(struct drm_device *dev)
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else
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hsw_shared_dplls_init(dev_priv);
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DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
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dev_priv->display.get_display_clock_speed(dev));
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cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
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DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq);
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if (IS_SKYLAKE(dev)) {
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dev_priv->skl_boot_cdclk = cdclk_freq;
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if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
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DRM_ERROR("LCPLL1 is disabled\n");
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else
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intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
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} else if (IS_BROXTON(dev)) {
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broxton_init_cdclk(dev);
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broxton_ddi_phy_init(dev);
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@ -5527,6 +5527,214 @@ void broxton_uninit_cdclk(struct drm_device *dev)
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intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
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}
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static const struct skl_cdclk_entry {
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unsigned int freq;
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unsigned int vco;
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} skl_cdclk_frequencies[] = {
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{ .freq = 308570, .vco = 8640 },
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{ .freq = 337500, .vco = 8100 },
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{ .freq = 432000, .vco = 8640 },
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{ .freq = 450000, .vco = 8100 },
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{ .freq = 540000, .vco = 8100 },
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{ .freq = 617140, .vco = 8640 },
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{ .freq = 675000, .vco = 8100 },
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};
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static unsigned int skl_cdclk_decimal(unsigned int freq)
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{
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return (freq - 1000) / 500;
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}
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static unsigned int skl_cdclk_get_vco(unsigned int freq)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
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const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
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if (e->freq == freq)
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return e->vco;
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}
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return 8100;
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}
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static void
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skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
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{
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unsigned int min_freq;
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u32 val;
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/* select the minimum CDCLK before enabling DPLL 0 */
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val = I915_READ(CDCLK_CTL);
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val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
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val |= CDCLK_FREQ_337_308;
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if (required_vco == 8640)
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min_freq = 308570;
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else
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min_freq = 337500;
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val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
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I915_WRITE(CDCLK_CTL, val);
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POSTING_READ(CDCLK_CTL);
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/*
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* We always enable DPLL0 with the lowest link rate possible, but still
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* taking into account the VCO required to operate the eDP panel at the
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* desired frequency. The usual DP link rates operate with a VCO of
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* 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
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* The modeset code is responsible for the selection of the exact link
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* rate later on, with the constraint of choosing a frequency that
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* works with required_vco.
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*/
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val = I915_READ(DPLL_CTRL1);
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val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
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DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
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val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
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if (required_vco == 8640)
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val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
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SKL_DPLL0);
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else
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val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
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SKL_DPLL0);
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I915_WRITE(DPLL_CTRL1, val);
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POSTING_READ(DPLL_CTRL1);
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I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
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if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
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DRM_ERROR("DPLL0 not locked\n");
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}
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static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
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{
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int ret;
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u32 val;
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/* inform PCU we want to change CDCLK */
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val = SKL_CDCLK_PREPARE_FOR_CHANGE;
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mutex_lock(&dev_priv->rps.hw_lock);
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ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
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mutex_unlock(&dev_priv->rps.hw_lock);
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return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
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}
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static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
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{
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unsigned int i;
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for (i = 0; i < 15; i++) {
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if (skl_cdclk_pcu_ready(dev_priv))
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return true;
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udelay(10);
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}
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return false;
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}
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static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
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{
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u32 freq_select, pcu_ack;
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DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
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if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
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DRM_ERROR("failed to inform PCU about cdclk change\n");
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return;
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}
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/* set CDCLK_CTL */
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switch(freq) {
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case 450000:
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case 432000:
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freq_select = CDCLK_FREQ_450_432;
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pcu_ack = 1;
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break;
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case 540000:
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freq_select = CDCLK_FREQ_540;
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pcu_ack = 2;
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break;
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case 308570:
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case 337500:
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default:
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freq_select = CDCLK_FREQ_337_308;
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pcu_ack = 0;
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break;
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case 617140:
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case 675000:
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freq_select = CDCLK_FREQ_675_617;
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pcu_ack = 3;
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break;
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}
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I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
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POSTING_READ(CDCLK_CTL);
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/* inform PCU of the change */
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mutex_lock(&dev_priv->rps.hw_lock);
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sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
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mutex_unlock(&dev_priv->rps.hw_lock);
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}
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void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
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{
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/* disable DBUF power */
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I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
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POSTING_READ(DBUF_CTL);
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udelay(10);
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if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
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DRM_ERROR("DBuf power disable timeout\n");
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/* disable DPLL0 */
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I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
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if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
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DRM_ERROR("Couldn't disable DPLL0\n");
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intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
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}
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void skl_init_cdclk(struct drm_i915_private *dev_priv)
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{
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u32 val;
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unsigned int required_vco;
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/* enable PCH reset handshake */
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val = I915_READ(HSW_NDE_RSTWRN_OPT);
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I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
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/* enable PG1 and Misc I/O */
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intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
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/* DPLL0 already enabed !? */
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if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
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DRM_DEBUG_DRIVER("DPLL0 already running\n");
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return;
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}
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/* enable DPLL0 */
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required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
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skl_dpll0_enable(dev_priv, required_vco);
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/* set CDCLK to the frequency the BIOS chose */
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skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
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/* enable DBUF power */
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I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
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POSTING_READ(DBUF_CTL);
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udelay(10);
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if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
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DRM_ERROR("DBuf power enable timeout\n");
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}
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/* returns HPLL frequency in kHz */
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static int valleyview_get_vco(struct drm_i915_private *dev_priv)
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{
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@ -1118,6 +1118,8 @@ void broxton_ddi_phy_init(struct drm_device *dev);
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void broxton_ddi_phy_uninit(struct drm_device *dev);
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void bxt_enable_dc9(struct drm_i915_private *dev_priv);
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void bxt_disable_dc9(struct drm_i915_private *dev_priv);
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void skl_init_cdclk(struct drm_i915_private *dev_priv);
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void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
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void intel_dp_get_m_n(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config);
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void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
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