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ARM: i.MX5: Add PATA and SRTC clocks 

This adds the clock gates and the binding documentation
for PATA and SRTC.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Sascha Hauer 2013-04-04 11:25:08 +02:00 committed by Shawn Guo
parent dc13ba2950
commit 5d530bb0ad
2 changed files with 5 additions and 0 deletions
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2
Documentation/devicetree/bindings/clock/imx5-clock.txt
View File

@ -183,6 +183,8 @@ clocks and IDs.
cko2_sel 168 cko2_sel 168
cko2_podf 169 cko2_podf 169
cko2 170 cko2 170
srtc_gate 171
pata_gate 172
Examples (for mx53): Examples (for mx53):

3
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -110,6 +110,7 @@ enum imx5_clks {
owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate, owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
cko1_sel, cko1_podf, cko1, cko1_sel, cko1_podf, cko1,
cko2_sel, cko2_podf, cko2, cko2_sel, cko2_podf, cko2,
srtc_gate, pata_gate,
clk_max clk_max
}; };
@ -266,6 +267,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
for (i = 0; i < ARRAY_SIZE(clk); i++) for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i])) if (IS_ERR(clk[i]))