Merge branch 'clockevents/fixes' of git://git.linaro.org/people/daniel.lezcano/linux into timers/urgent
Pull clockevents/clocksource fixes from Daniel Lezcano: * Axel Lin added a missing dependency on CLKSRC_MMIO in the Kconfig for the time-efm32 * Dinh Nguyen fixed read_sched_clock to return the right value and added the clksrc-of missing definition for the dw_apb_timer * Ezequiel Garcia registered the sched clock after the counter, thus preventing time jump in the traces for the armada-370-xp * Marc Zyngier stopped the timer before enabling the irq in order to prevent it to be fired before the clockevent is registered for the sunxi * Thierry Reding removed a of_node_put in clksrc-of because the reference is not held Signed-off-by: Ingo Molnar <mingo@kernel.org>
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commit
5d5119a476
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@ -75,6 +75,7 @@ config CLKSRC_DBX500_PRCMU_SCHED_CLOCK
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config CLKSRC_EFM32
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bool "Clocksource for Energy Micro's EFM32 SoCs" if !ARCH_EFM32
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depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST)
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select CLKSRC_MMIO
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default ARCH_EFM32
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help
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Support to use the timers of EFM32 SoCs as clock source and clock
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@ -35,6 +35,5 @@ void __init clocksource_of_init(void)
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init_func = match->data;
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init_func(np);
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of_node_put(np);
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}
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}
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@ -108,12 +108,11 @@ static void __init add_clocksource(struct device_node *source_timer)
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static u64 read_sched_clock(void)
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{
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return __raw_readl(sched_io_base);
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return ~__raw_readl(sched_io_base);
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}
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static const struct of_device_id sptimer_ids[] __initconst = {
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{ .compatible = "picochip,pc3x2-rtc" },
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{ .compatible = "snps,dw-apb-timer-sp" },
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{ /* Sentinel */ },
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};
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@ -151,4 +150,6 @@ static void __init dw_apb_timer_init(struct device_node *timer)
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num_called++;
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}
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CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
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CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer-osc", dw_apb_timer_init);
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CLOCKSOURCE_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init);
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CLOCKSOURCE_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init);
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CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init);
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@ -179,6 +179,9 @@ static void __init sun4i_timer_init(struct device_node *node)
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writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
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timer_base + TIMER_CTL_REG(0));
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/* Make sure timer is stopped before playing with interrupts */
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sun4i_clkevt_time_stop(0);
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ret = setup_irq(irq, &sun4i_timer_irq);
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if (ret)
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pr_warn("failed to setup irq %d\n", irq);
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@ -255,11 +255,6 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
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ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
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/*
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* Set scale and timer for sched_clock.
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*/
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sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
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/*
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* Setup free-running clocksource timer (interrupts
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* disabled).
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@ -270,6 +265,11 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
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timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN |
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TIMER0_DIV(TIMER_DIVIDER_SHIFT));
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/*
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* Set scale and timer for sched_clock.
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*/
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sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
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clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
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"armada_370_xp_clocksource",
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timer_clk, 300, 32, clocksource_mmio_readl_down);
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