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KVM: PPC: Book3S HV: Update LPID allocator init for POWER9, Nested 

The LPID allocator init is changed to:
- use mmu_lpid_bits rather than hard-coding;
- use KVM_MAX_NESTED_GUESTS for nested hypervisors;
- not reserve the top LPID on POWER9 and newer CPUs.

The reserved LPID is made a POWER7/8-specific detail.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220123120043.3586018-3-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin 2022-01-23 22:00:39 +10:00 committed by Michael Ellerman
parent 18827eeef0
commit 5d506f159b
5 changed files with 33 additions and 11 deletions
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2
arch/powerpc/include/asm/kvm_book3s_asm.h
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@ -15,7 +15,7 @@
#define XICS_IPI 2 /* interrupt source # for IPIs */
/* LPIDs we support with this build -- runtime limit may be lower */
#define KVMPPC_NR_LPIDS (LPID_RSVD + 1)
#define KVMPPC_NR_LPIDS (1UL << 12)
/* Maximum number of threads per physical core */
#define MAX_SMT_THREADS 8

2
arch/powerpc/include/asm/reg.h
View File

@ -473,8 +473,6 @@
#ifndef SPRN_LPID
#define SPRN_LPID 0x13F /* Logical Partition Identifier */
#endif
#define LPID_RSVD_POWER7 0x3ff /* Reserved LPID for partn switching */
#define LPID_RSVD 0xfff /* Reserved LPID for partn switching */
#define SPRN_HMER 0x150 /* Hypervisor maintenance exception reg */
#define HMER_DEBUG_TRIG (1ul << (63 - 17)) /* Debug trigger */
#define SPRN_HMEER 0x151 /* Hyp maintenance exception enable reg */

29
arch/powerpc/kvm/book3s_64_mmu_hv.c
View File

@ -256,7 +256,7 @@ void kvmppc_map_vrma(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot,
int kvmppc_mmu_hv_init(void)
{
unsigned long rsvd_lpid;
unsigned long nr_lpids;
if (!mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE))
return -EINVAL;
@ -264,16 +264,29 @@ int kvmppc_mmu_hv_init(void)
if (cpu_has_feature(CPU_FTR_HVMODE)) {
if (WARN_ON(mfspr(SPRN_LPID) != 0))
return -EINVAL;
nr_lpids = 1UL << mmu_lpid_bits;
} else {
nr_lpids = KVM_MAX_NESTED_GUESTS;
}
/* POWER8 and above have 12-bit LPIDs (10-bit in POWER7) */
if (cpu_has_feature(CPU_FTR_ARCH_207S))
rsvd_lpid = LPID_RSVD;
else
rsvd_lpid = LPID_RSVD_POWER7;
if (nr_lpids > KVMPPC_NR_LPIDS)
nr_lpids = KVMPPC_NR_LPIDS;
/* rsvd_lpid is reserved for use in partition switching */
kvmppc_init_lpid(rsvd_lpid);
if (!cpu_has_feature(CPU_FTR_ARCH_300)) {
/* POWER7 has 10-bit LPIDs, POWER8 has 12-bit LPIDs */
if (cpu_has_feature(CPU_FTR_ARCH_207S))
WARN_ON(nr_lpids != 1UL << 12);
else
WARN_ON(nr_lpids != 1UL << 10);
/*
* Reserve the last implemented LPID use in partition
* switching for POWER7 and POWER8.
*/
nr_lpids -= 1;
}
kvmppc_init_lpid(nr_lpids);
return 0;
}

8
arch/powerpc/kvm/book3s_hv_rmhandlers.S
View File

@ -50,6 +50,14 @@
#define STACK_SLOT_UAMOR (SFS-88)
#define STACK_SLOT_FSCR (SFS-96)
/*
* Use the last LPID (all implemented LPID bits = 1) for partition switching.
* This is reserved in the LPID allocator. POWER7 only implements 0x3ff, but
* we write 0xfff into the LPID SPR anyway, which seems to work and just
* ignores the top bits.
*/
#define LPID_RSVD 0xfff
/*
* Call kvmppc_hv_entry in real mode.
* Must be called with interrupts hard-disabled.

3
arch/powerpc/mm/init_64.c
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@ -372,6 +372,9 @@ void register_page_bootmem_memmap(unsigned long section_nr,
#ifdef CONFIG_PPC_BOOK3S_64
unsigned int mmu_lpid_bits;
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
EXPORT_SYMBOL_GPL(mmu_lpid_bits);
#endif
unsigned int mmu_pid_bits;
static bool disable_radix = !IS_ENABLED(CONFIG_PPC_RADIX_MMU_DEFAULT);