thermal: exynos: remove needless tmu_status abstraction
reg->tmu_status is used only in exynos_tmu_initialize() and it is accessed only if TMU_SUPPORT_READY_STATUS flag is set. This flag is not set for Exynos5440 and TMU_STATUS register offset is identical for all other SoC types so the abstraction is not needed and can be removed. There should be no functional changes caused by this patch. Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
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@ -154,7 +154,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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clk_enable(data->clk_sec);
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if (TMU_SUPPORTS(pdata, READY_STATUS)) {
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status = readb(data->base + reg->tmu_status);
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status = readb(data->base + EXYNOS_TMU_REG_STATUS);
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if (!status) {
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ret = -EBUSY;
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goto out;
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@ -83,7 +83,6 @@ enum soc_type {
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* @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
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* @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
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* @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
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* @tmu_status: register drescribing the TMU status.
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* @tmu_cur_temp: register containing the current temperature of the TMU.
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* @threshold_temp: register containing the base threshold level.
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* @threshold_th0: Register containing first set of rising levels.
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@ -115,8 +114,6 @@ struct exynos_tmu_registers {
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u32 therm_trip_mode_mask;
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u32 therm_trip_en_shift;
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u32 tmu_status;
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u32 tmu_cur_temp;
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u32 threshold_temp;
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@ -27,7 +27,6 @@
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#if defined(CONFIG_CPU_EXYNOS4210)
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static const struct exynos_tmu_registers exynos4210_tmu_registers = {
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
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.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
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@ -92,7 +91,6 @@ static const struct exynos_tmu_registers exynos3250_tmu_registers = {
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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@ -173,7 +171,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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@ -263,7 +260,6 @@ static const struct exynos_tmu_registers exynos5260_tmu_registers = {
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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@ -341,7 +337,6 @@ static const struct exynos_tmu_registers exynos5420_tmu_registers = {
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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@ -427,7 +422,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
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.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
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.threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
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.threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
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@ -88,7 +88,6 @@
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#define EXYNOS5440_TMU_S0_7_TRIM 0x000
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#define EXYNOS5440_TMU_S0_7_CTRL 0x020
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#define EXYNOS5440_TMU_S0_7_DEBUG 0x040
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#define EXYNOS5440_TMU_S0_7_STATUS 0x060
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#define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
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#define EXYNOS5440_TMU_S0_7_TH0 0x110
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#define EXYNOS5440_TMU_S0_7_TH1 0x130
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