drm/amdgpu: expose peak profiling mode shader/memory clocks
Expose those informations to UMD who need them as for standard profiling mode. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1014,6 +1014,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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}
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ui32 /= 100;
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break;
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case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
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/* get peak pstate sclk in Mhz */
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if (amdgpu_dpm_read_sensor(adev,
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AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
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(void *)&ui32, &ui32_size)) {
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return -EINVAL;
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}
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ui32 /= 100;
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break;
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case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
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/* get peak pstate mclk in Mhz */
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if (amdgpu_dpm_read_sensor(adev,
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AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
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(void *)&ui32, &ui32_size)) {
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return -EINVAL;
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}
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ui32 /= 100;
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break;
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default:
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DRM_DEBUG_KMS("Invalid request %d\n",
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info->sensor_info.type);
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@ -832,6 +832,10 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
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/* Subquery id: Query GPU stable pstate memory clock */
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#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
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/* Subquery id: Query GPU peak pstate shader clock */
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#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
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/* Subquery id: Query GPU peak pstate memory clock */
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#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
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/* Number of VRAM page faults on CPU access. */
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#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
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#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
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