drm/amdgpu: correct Arcturus SDMA address space base index
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -211,17 +211,17 @@ static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
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case 1:
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case 1:
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return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
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return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
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case 2:
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case 2:
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return (adev->reg_offset[SDMA2_HWIP][0][0] + offset);
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return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
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case 3:
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case 3:
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return (adev->reg_offset[SDMA3_HWIP][0][0] + offset);
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return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
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case 4:
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case 4:
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return (adev->reg_offset[SDMA4_HWIP][0][0] + offset);
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return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
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case 5:
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case 5:
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return (adev->reg_offset[SDMA5_HWIP][0][0] + offset);
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return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
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case 6:
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case 6:
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return (adev->reg_offset[SDMA6_HWIP][0][0] + offset);
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return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
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case 7:
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case 7:
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return (adev->reg_offset[SDMA7_HWIP][0][0] + offset);
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return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
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default:
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default:
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break;
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break;
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}
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}
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